模拟集成电路中的频率补偿

Feature

Two-Stage

Operational Amplifiers:

Power-and-Area-Efficient Frequency Compensation for Driving a Wide Range of Capacitive Load

© DIGITAL VISION

Digital Object Identifier 10.1109/MCAS.2010.939783Date of publication: 18 February 2011

26 IEEE CIRCUITS AND SYSTEMS MAGAZINE

1531-636X/11/$26.00©2011 IEEE FIRST QUARTER 2011

Abstract

Operational amplifiers (OpAmps) have found exten-sive applications in analog circuits and systems for communications, consumer electronics, controls and signal conversion. Two-stage OpAmps with frequency compensation are popular for driving capacitive loads while ensuring sufficient gain and stability. Frequen-cy compensation techniques have been evolving over the last decades in distinct applications. In particular, power-and-area-efficent two-stage OpAmps capable of driving a wide-range capacitive load are demanded for low-dropout regulators (LDOs) or LCD-panel drivers. Capacitor multiplers (CMs) have emerged as one of the best solutions to implement such kind of OpAmps.

This article reviews, for the first time, the state-of-the-art CMs for two-stage OpAmps before describing a novel embedded-CM technique, i.e., the CM as being part of the input stage of the OpAmp, effectively mini-mizing the physical size of the compensation capaci-tors while improving the slew-rate with no extra pow-er consumption. Moreover, unlike the classical Miller compensation technique that can lead to an undesired right-half-plane (RHP) zero, a constructive left-half-plane (LHP) zero, is created, that can improve the phase margin (PM). Comparing with the state-of-the-art current-buffer and CM compensation topologies the proposed solution also features simpler circuitry. The technique can be further incorporated with a class-AB output stage to speed up the OpAmp’s transient re-sponses with low quiescent power. A descriptive design example capable of driving capacitive loads $ 50 pF is systematically optimized in a 0.35-mm CMOS process. Finally, a few techniques are outlined which allow the combination of current-buffer-based Miller compensa-tion with more sophisticated CMs, or a pole-zero pair (lead network), to further enhance the driving capabil-ity of two-stage OpAmps.

O

I. Introduction

perational amplifiers (OpAmps) have been at the core of a wide range of analog circuits such as analog-to-digital converters, low-dropout regula-tors (LDOs) and active filters [1]. Portable systems, as the wireless transceivers, integrate most of these func-tions, appealing for more high-performance OpAmps to meet the increasingly tight power and area budgets. Par-ticularly, OpAmps for LCD panels or headphone drivers require a wide-range capacitive load driving capability [2]–[3]. A low-quiescent-power small-area OpAmp that supports a wide range of load capacitance constitutes the motivation of improving the existing frequency com-pensation techniques. The conventional multi-stage OpAmp topology (gain stages $3) does not appear as a wise choice since the frequency compensation leads to large reduction of the gain-bandwidth (GBW) product, and almost none of the published topologies are suit-able for driving a wide range of capacitive load with low-power consumption [4]. On the other hand, a two-stage OpAmp topology [Fig. 1(a)] is selected as it exhibits more sensible and simpler tradeoffs among the DC gain, GBW, quiescent power and output swing. As it is well known, two-stage OpAmps also require frequency com-pensation to obtain a stable closed-loop operation. How-ever, to the authors’ knowledge, during the past several decades only four compensation schemes shown in Fig. 1(b)–(e) have been developed, mainly with the aim of eliminating the right-half-plane (RHP) zero as shown in Fig. 1(a), rather than handling highly variable capacitive loads [5]–[18]. To choose an optimum topology coping with this challenge, the local feedback loops of these circuit structures can be interpreted as being able to cut the loops according to that in Fig. 1(a).

The magnitude plots of the loop gain T1s2 of the dif-ferent schemes (from Fig. 1) are given in Fig. 2. Com-paring them, SMC, MCVB, MCNR, and MCFT have the same unity-gain frequency (UGF) vm while the UGF of MCCB is Cm/Cp1 times higher than them under the same configuration of circuit parameters. The abundant UGF of MCCB can be used to trade for small power and area. Therefore, MCCB is essentially more power-and-area efficient than other compensation schemes, though the capability of driving small capacitive loads is lim-ited by the parasitic pole 1CL1Cm2/1RcCLCm2 generated by the current buffer. Another issue associated with MCCB is related with the fact that when the capacitive load is heavy, in the order of hundreds of pF, the com-pensation capacitor Cm must be set to a large value for driving the load, and more importantly maintaining a reasonable gain of the first stage [19]. Moreover, large Cm not only occupies a great amount of silicon area but significantly lowers the OpAmp’s slew rate. A feasible solution to overcome this difficulty utilizes capacitor-multipliers (CMs), since CMs minimize the physical size of the capacitors while retaining the effective

Zushu Yan, Pui-In Mak and Rui P. Martins are with the State-Key Laboratory of Analog and Mixed-Signal VLSI, FST, University of Macau, Macao, China.

1

On leave from Instituto Superior Técnico (IST)/TU of Lisbon, Portugal. Corresponding E-mail: pimak@umac.mo

FIRST QUARTER 2011

IEEE CIRCUITS AND SYSTEMS MAGAZINE

27

capacitance required. Until now, many effective CMs have been proposed. For instance, in [20], a current-mode CM based on current mirrors was reported. However, this method still cannot achieve a high mul-tiplication factor owing to the power and bandwidth constraints. Although the approaches from [21]–[23] boost the multiplication fact …… 此处隐藏：6271字，全部文档内容请下载后查看。喜欢就下载吧 ……