TMS320C64x DSP Two Level Internal Memory Reference Guide (Re(6)

locations it can map to in a 4-way set-associative cache.ThrashTouchValidVictimVictim BufferVictim WritebackWay

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Cache Terms and Definitions

Table 2.

Term

Working setTerms and Definitions (Continued)DefinitionThe working set for a program or algorithm is the total set of data and program code

that is referenced within a particular period of time. It is often useful to consider theworking set on an algorithm-by-algorithm basis when analyzing upper levels of

memory, and on a whole-program basis when analyzing lower levels of memory.

A write-allocate cache allocates space in the cache when a write miss occurs. Space

is allocated according to the cache’s allocation policy (LRU, for example), and the

data for the line is read into the cache from the next lower level of memory. Once the

data is present in the cache, the write is processed. For a writeback cache, only the

current level of memory is updated—the write data is not immediately passed to the

next level of memory.

The process of writing updated data from a valid but dirty cache line to a lower-level

memory. After the writeback occurs, the cache line is considered clean. Unless

paired with an invalidate (as in writeback-invalidate), the line remains valid after a

writeback.

A writeback cache will only modify its own data on a write hit. It will not immediately

send the update to the next lower-level of memory. The data will be written back at

some future point, such as when the cache line is evicted, or when the lower-level

memory snoops the address from the higher-level memory. It is also possible to

directly initiate a writeback for a range of addresses using cache control registers. A

write hit to a writeback cache causes the corresponding line to be marked as

dirty—that is, the line contains updates that have yet to be sent to the lower levels of

memory.

A writeback operation followed by an invalidation. See writeback and invalidate. On

the C64x devices, a writeback-invalidate on a group of cache lines only writes out

data for dirty cache lines, but invalidates the contents of all of the affected cache lines.

Write merging combines multiple independent writes into a single, larger write. This

improves the performance of the memory system by reducing the number of

individual memory accesses it needs to process. For instance, on the C64x device,

the L1D write buffer can merge multiple writes under some circumstances if they are

to the same double-word address. In this example, the result is a larger effective

write-buffer capacity and a lower bandwidth impact on L2.

A write-through cache passes all writes to the lower-level memory. It never contains

updated data that it has not passed on to the lower-level memory. As a result, cache

lines can never be dirty in a write-through cache. The C64x devices do not utilize

write-through caches.Write allocateWritebackWriteback cacheWriteback-invalidateWrite mergingWrite-through cache

18TMS320C64x Two-Level Internal MemorySPRU610B

Level 1 Data Cache (L1D)

3Level 1 Data Cache (L1D)

The level 1 data cache (L1D) services data accesses from the CPU. The

following sections describe the parameters and operation of the L1D. Theoperation of L1D is controlled by various registers, as described in section 7,Memory System Controls.

3.1L1D Parameters

The L1D is a 16K-byte cache. It is a two-way set associative cache with a

64-byte line size and 128 sets. It also features a 64-bit by 4-entry write buffer

between L1D and the L2 memory.

Physical addresses map onto the cache in a straightforward manner. The

physical address divides into three fields as shown in Figure 3. Bits 5 0 of the

address specify an offset within the line. Bits 12 6 of the address select one

of the 128 sets within the cache. Bits 31 13 of the address serve as the tag

for the line.

Figure 3.

31L1D Address Allocation1312

TagSet Index65Offset0

Because L1D is a two-way cache, each set contains two cache lines, one for

each way. On each access, the L1D compares the tag portion of the address

for the access to the tag information for both lines in the appropriate set. If the

tag matches one of the lines and that line is marked valid, the access is a hit.

If these conditions are not met, the access is a miss. Miss penalties are

discussed in detail under section 3.2.

The L1D is a read-allocate-only cache. This means that new lines are allocated

in L1D for read misses, but not for write misses. For this reason, a 4-entry write

buffer exists between the L1D and L2 caches that captures data from write

misses. The write buffer is enhanced in comparison to the write buffer on the

C621x/C671x devices. The write buffer is described in section 3.2.3.

The L1D implements a least-recently used (LRU) line allocation policy. This

means that on an L1D read miss, the L1D evicts the least-recently read or

written line within a set in order to make room for the incoming data. Note that

invalid lines are always considered least-recently used.

If the selected line is dirty, that is, its contents are updated, then the victim line’s

data is prepared for writeback to L2 as a victim writeback. The actual victim

writeback occurs after the new data is fetched, and then only if the newly

fetched data is considered cacheable. If the newly fetched data is

noncacheable, the victim writeback is cancelled and the victim line remains in

the L1D cache.

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