TMS320C64x DSP Two Level Internal Memory Reference Guide (Re(4)

SPRU610BTMS320C64x Two-Level Internal Memory11

Memory Hierarchy Overview

Figure 2.TMS320C64x Two-Level Internal Memory Block Diagram

12TMS320C64x Two-Level Internal MemorySPRU610B

Cache Terms and Definitions

2Cache Terms and Definitions

Table 2 lists the terms used throughout this document that relate to the

operation of the C64x two-level memory hierarchy.

Table 2.

Term

AllocationTerms and Definitions DefinitionThe process of finding a location in the cache to store newly cached data. This

process can include evicting data that is presently in the cache to make room for the

new data.

The number of line frames in each set. This is specified as the number of ways in the

cache.

A cache miss that occurs because the cache does not have sufficient room to hold the

entire working set for a program. Compare with compulsory miss and conflict miss.

A cache line that is valid and that has not been written to by upper levels of memory

or the CPU. The opposite state for a valid cache line is dirty.

Informally, a memory system is coherent if any read of a data item returns the most

recently written value of that data item. This includes accesses by the CPU and theEDMA. Cache coherence is covered in more detail in section 8.1.

Sometimes referred to as a first-reference miss. A compulsory miss is a cache miss

that must occur because the data has had no prior opportunity to be allocated in the

cache. Typically, compulsory misses for particular pieces of data occur on the first

access of that data. However, some cases can be considered compulsory even if

they are not the first reference to the data. Such cases include repeated write misses

on the same location in a cache that does not write allocate, and cache misses to

noncacheable locations. Compare with capacity miss and conflict miss.

A cache miss that occurs due to the limited associativity of a cache, rather than due

to capacity constraints. A fully-associative cache is able to allocate a newly cached

line of data anywhere in the cache. Most caches have much more limited

associativity (see set-associative cache), and so are restricted in where they may

place data. This results in additional cache misses that a more flexible cache would

not experience.

A direct-mapped cache maps each address in the lower-level memory to a single

location in the cache. Multiple locations may map to the same location in the cache.

This is in contrast to a multi-way set-associative cache, which selects a place for the

data from a set of locations in the cache. A direct-mapped cache can be considered

a single-way set-associative cache.

In a writeback cache, writes that reach a given level in the memory hierarchy may

update that level, but not the levels below it. Thus, when a cache line is valid and

contains updates that have not been sent to the next lower level, that line is said to

be dirty. The opposite state for a valid cache line is clean.AssociativityCapacity missCleanCoherenceCompulsory missConflict missDirect-mapped cacheDirty

SPRU610BTMS320C64x Two-Level Internal Memory13

Cache Terms and Definitions

Table 2.

Term

DMATerms and Definitions (Continued)DefinitionDirect Memory Access. Typically, a DMA operation copies a block of memory from

one range of addresses to another, or transfers data between a peripheral and

memory. On the C64x DSP, DMA transfers are performed by the enhanced DMA

(EDMA) engine. These DMA transfers occur in parallel to program execution. From a

cache coherence standpoint, EDMA accesses can be considered accesses by a

parallel processor.

The process of removing a line from the cache to make room for newly cached data.

Eviction can also occur under user control by requesting a writeback-invalidate for an

address or range of addresses from the cache. The evicted line is referred to as the

victim. When a victim line is dirty (that is, it contains updated data), the data must be

written out to the next level memory to maintain coherency.

A block of instructions that begin execution in parallel in a single cycle. An execute

packet may contain between 1 and 8 instructions.

A block of 8 instructions that are fetched in a single cycle. One fetch packet may

contain multiple execute packets, and thus may be consumed over multiple cycles.

A cache miss that occurs on the first reference to a piece of data. First-reference

misses are a form of compulsory miss.

A cache that allows any memory address to be stored at any location within the

cache. Such caches are very flexible, but usually not practical to build in hardware.

They contrast sharply with direct-mapped caches and set-associative caches, both of

which have much more restrictive allocation policies. Conceptually, fully-associative

caches are useful for distinguishing between conflict misses and capacity misses

when analyzing the performance of a direct-mapped or set-associative cache. In

terms of set-associative caches, a fully-associative cache is equivalent to a

set-associative cache that has as many ways as it does line frames, and that has

only one set.

In a hierarchical memory system, higher-level memories are memories that are

closer to the CPU. The highest level in the memory hierarchy is usually the Level 1

caches. The memories at this level exist directly next to the CPU. Higher-level

memories typically act as caches for data from lower-level memory.

A cache hit occurs when the data for a requested memory location is present in the

cache. The opposite of a hit is a miss. A cache hit minimizes stalling, since the data