TMS320C64x DSP Two Level Internal Memory Reference Guide (Re(3)

TMS320C64x Two-Level Internal Memory7SPRU610B

Tables

Tables

1TMS320C621x/C671x/C64x Internal Memory Comparison. . . . . . . . . . . . . . . . . . . . . . . . . . 102Terms and Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133Cycles Per Miss for Different Numbers of L1D Misses That Hit L2 Cache. . . . . . . . . . . . . . 264Cycles Per Miss for Different Numbers of L1D Misses that Hit L2 SRAM. . . . . . . . . . . . . . . 265Average Miss Penalties for Large Numbers of Sequential Execute Packets. . . . . . . . . . . . 296Internal Memory Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387Cache Configuration Register (CCFG) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . 398L2 EDMA Access Control Register (EDMAWEIGHT) Field Descriptions. . . . . . . . . . . . . . . 419L2 Allocation Registers (L2ALLOC0 L2ALLOC3) Field Descriptions. . . . . . . . . . . . . . . . . . 4210L2 Writeback Base Address Register (L2WBAR) Field Descriptions. . . . . . . . . . . . . . . . . . . 4311L2 Writeback Word Count Register (L2WWC) Field Descriptions. . . . . . . . . . . . . . . . . . . . . 4312L2 Writeback Invalidate Base Address Register (L2WIBAR) Field Descriptions. . . . . . . . 4413L2 Writeback Invalidate Word Count Register (L2WIWC) Field Descriptions. . . . . . . . . . . 4414L2 Invalidate Base Address Register (L2IBAR) Field Descriptions. . . . . . . . . . . . . . . . . . . . 4515L2 Invalidate Word Count Register (L2IWC) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . 4516L1P Invalidate Base Address Register (L1PIBAR) Field Descriptions. . . . . . . . . . . . . . . . . 4617L1P Invalidate Word Count Register (L1PIWC) Field Descriptions. . . . . . . . . . . . . . . . . . . . 4618L1D Writeback Invalidate Base Address Register (L1DWIBAR) Field Descriptions. . . . . 4719L1D Writeback Invalidate Word Count Register (L1DWIWC) Field Descriptions. . . . . . . . 4720L1D Invalidate Base Address Register (L1DIBAR) Field Descriptions. . . . . . . . . . . . . . . . . 4821L1D Invalidate Word Count Register (L1DIWC) Field Descriptions. . . . . . . . . . . . . . . . . . . . 4822L2 Writeback All Register (L2WB) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4923L2 Writeback Invalidate All Register (L2WBINV) Field Descriptions. . . . . . . . . . . . . . . . . . . 5024Memory Attribute Register (MAR) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5125L1D Mode Setting Using DCC Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5226L1P Mode Setting Using PCC Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5327L2 Mode Switch Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5528Memory Attribute Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5729Summary of Program-Initiated Cache Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6030L2ALLOC Default Queue Allocations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6831Coherence Assurances in the Two-Level Memory System. . . . . . . . . . . . . . . . . . . . . . . . . . . 7032Program Order for Memory Operations Issued From a Single Execute Packet. . . . . . . . . 7633Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818T MS320C64x Two-Level Internal MemorySPRU610B

TMS320C64x Two-Level Internal Memory

The TMS320C621x, TMS320C671x, and TMS320C64x digital signal

processors (DSPs) of the TMS320C6000 DSP family have a two-level

memory architecture for program and data. The first-level program cache is

designated L1P, and the first-level data cache is designated L1D. Both the

program and data memory share the second-level memory, designated L2. L2

is configurable, allowing for various amounts of cache and SRAM. This

document discusses the C64x two-level internal memory. For a discussion

of the C621x/C671x two-level internal memory, see TMS320C621x/C671x DSP

Two-Level Internal Memory Reference Guide (SPRU609).

1Memory Hierarchy Overview

Figure 1 shows the block diagram of the C64x DSP. Table 1 summarizes the

differences between the C621x/C671x and C64x internal memory. Figure 2

illustrates the bus connections between the CPU, internal memories, and the

enhanced DMA (EDMA) of the C6000 DSP.

Figure 1.

TMS320C64x DSP Block Diagram

Note:EMIFB is available only on certain C64x devices. Refer to the device-specific data sheet for the available peripheral set.SPRU610BTMS320C64x Two-Level Internal Memory9

Memory Hierarchy Overview

Table 1.TMS320C621x/C671x/C64x Internal Memory Comparison

TMS320C621x/C671x DSPTMS320C64x DSP

Internal memory structureL1P size

L1P organization

L1P CPU access time

L1P line size

L1P read miss action

L1P read hit action

L1P write miss action

L1P write hit action

L1P → L2 request size

L1P protocol

L1P memory

L1P → L2 single request stall

L1P → L2 minimum cycles between

pipelined misses

L1D size

L1D organization

L1D CPU access time

L1D line size

L1D replacement strategy

L1D banking

L1D read miss action

L1D read hit action

L1D write miss action

L1D write hit action

L1D protocol

L1D → L2 request size

Two Level4 KbytesDirect mapped1 cycle64 bytes1 line allocated in L1PData read from L1PL1P writes not supportedL1P writes not supporte …… 此处隐藏：5868字，全部文档内容请下载后查看。喜欢就下载吧 ……