TMS320C64x DSP Two Level Internal Memory Reference Guide (Re(5)

When a CPU request misses both the first-level and second-level caches, the data is

fetched from the external memory and stored to both the first-level and second-level

cache simultaneously. A cache that stores data and sends that data to the

upper-level cache at the same time is a load-through cache. Using a load-through

cache reduces the stall time compared to a cache that first stores the data in a lower

level and then sends it to the higher-level cache as a second step.Least Recently Used(LRU) allocationLineLine frameLine sizeLoad through

Long-distance accessAccesses made by the CPU to a noncacheable memory. Long-distance accesses

are used when accessing external memory that is not marked as cacheable.

Lower-level memoryIn a hierarchical memory system, lower-level memories are memories that are further

from the CPU. In a C64x system, the lowest level in the hierarchy includes the

system memory below L2 and any memory-mapped peripherals.

Least Recently Used. See least recently used allocation for a description of the LRU

replacement policy. When used alone, LRU usually refers to the status information

that the cache maintains for identifying the least-recently used line in a set. For

example, consider the phrase “accessing a cache line updates the LRU for that line.”LRU

SPRU610BTMS320C64x Two-Level Internal Memory15

Cache Terms and Definitions

Table 2.

TermTerms and Definitions (Continued)Definition

Defines what order the effects of memory operations are made visible in memory.

(This is sometimes referred to as consistency.) Strong memory ordering at a given

level in the memory hierarchy indicates it is not possible to observe the effects of

memory accesses in that level of memory in an order different than program order.

Relaxed memory ordering allows the memory hierarchy to make the effects of

memory operations visible in a different order. Note that strong ordering does not

require that the memory system execute memory operations in program order, only

that it makes their effects visible to other requestors in an order consistent withprogram order. Section 8.3 covers the memory ordering assurances that the C64x

memory hierarchy provides.

A cache miss occurs when the data for a requested memory location is not in the

cache. A miss may stall the requestor while the line frame is allocated and data is

fetched from the next lower level of memory. In some cases, such as a CPU write

miss from L1D, it is not strictly necessary to stall the CPU. Cache misses are often

divided into three categories: compulsory misses, conflict misses, and capacity

misses.

The process of servicing a single cache miss is pipelined over several cycles. By

pipelining the miss, it is possible to overlap the processing of several misses, should

many occur back-to-back. The net result is that much of the overhead for the

subsequent misses is hidden, and the incremental stall penalty for the additional

misses is much smaller than that for a single miss taken in isolation.

A read-allocate cache only allocates space in the cache on a read miss. A write miss

does not cause an allocation to occur unless the cache is also a write-allocate cache.

For caches that do not write allocate, the write data would be passed on to the next

lower-level cache.

A collection of line frames in a cache that a single address can potentially reside. A

direct-mapped cache contains one line frame per set, and an N-way set-associative

cache contains N line frames per set. A fully-associative cache has only one set that

contains all of the line frames in the cache.

A set-associative cache contains multiple line frames that each lower-level memory

location can be held in. When allocating room for a new line of data, the selection is

made based on the allocation policy for the cache. The C64x devices employ a least

recently used allocation policy for its set-associative caches.

A method by which a lower-level memory queries a higher-level memory to

determine if the higher-level memory contains data for a given address. The primary

purpose of snoops is to retain coherency, by allowing a lower-level memory to

request updates from a higher-level memory. A snoop operation may trigger a

writeback, or more commonly, a writeback-invalidate. Snoops that trigger

writeback-invalidates are sometimes called snoop-invalidates.Memory orderingMissMiss pipeliningRead allocateSetSet-associativecacheSnoop

16TMS320C64x Two-Level Internal MemorySPRU610B

Cache Terms and Definitions

Table 2.

Term

TagTerms and Definitions (Continued)DefinitionA storage element containing the most-significant bits of the address stored in a

particular line. Tag addresses are stored in special tag memories that are not directly

visible to the CPU. The cache queries the tag memories on each access to

determine if the access is a hit or a miss.

An algorithm is said to thrash the cache when its access pattern causes the

performance of the cache to suffer dramatically. Thrashing can occur for multiple

reasons. One possible situation is that the algorithm is accessing too much data or

program code in a short time frame with little or no reuse. That is, its working set is

too large, and thus the algorithm is causing a significant number of capacity misses.

Another situation is that the algorithm is repeatedly accessing a small group of

different addresses that all map to the same set in the cache, thus causing an

artificially high number of conflict misses.

A memory operation on a given address is said to touch that address. Touch can also

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