ISL78010ANZ-T;ISL78010ANZ;中文规格书,Datasheet资料(2)

VVVnAmS%mA

VF_FBLIFBLGMLΔVLOGIC/ΔI(VLOGIC)IDRVLIL_DRL

SEQUENCINGtONtSStDEL1tDEL2IDELB

FBL Fault Trip PointFBL Input Bias Current

FBL Effective TransconductanceVLOGIC Load RegulationDRVL Sink Current MaxIL_DRVL

VFBL fallingVFBL = 1.35V

VDRVL = 2.5V, IDRVL = 1mA to 8mAI(VLOGIC) = 100mA to 500mAVFBL = 1.1V, VDRVL = 2.5VVFBL = 1.5V, VDRVL = 5.5V

2000.5

8

160.1

5

µA

Turn On DelaySoft-start Time

Delay Between AVDD and VOFFDelay Between VON and VOFFDELB Pull-down Current

CDLY = 0.22µFCDLY = 0.22µFCDLY = 0.22µFCDLY = 0.22µFVDELB>0.6VVDELB<0.6V

3021017501.4

msmsmsmsµAmA

ISL78010

Electrical Specifications

VDD = 5V, VBOOST = 11V, ILOAD = 200mA, VON = 15V, VOFF = -5V, VLOGIC = 2.5V, limits over -40°C to +105°C temperature range, unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +105°C. (Continued)

CONDITION

MIN(Note 6)

TYP

MAX(Note 6)

UNIT

PARAMETERFAULT DETECTIONtFAULTOTIPG

DESCRIPTION

Fault Time Out

Over-temperature ThresholdPG Pull-down Current

CDLY = 0.22µF

50140

ms°CµAmA

VPG>0.6VVPG<0.6V

151.7

LOGIC ENABLEVHIVLOILOWIHIGHNOTE:

6.Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested.

Logic High ThresholdLogic Low ThresholdLogic Low Bias CurrentLogic High Bias Current

at VEN = 5V

12

0.218

2.3

0.8224

VVµAµA

Pin Descriptions

PIN NAME1, 2, 4, 6, 8, 10, 12, 16, 18, 23, 32

3579111314, 27151719, 20, 21, 22

24252628293031

PIN NUMBER

NCDELBLXDRVPFBPDRVLFBLSGNDDRVNFBNPGNDVREFCINTFBBENVDDPG CDLY

Not connected

Open drain output for gate drive of optional VBOOST delay FETDrain of the internal N-Channel boost FET

Positive LDO base drive; open drain of an internal N-Channel FETPositive LDO voltage feedback input pin; regulates to 1.2V nominalLogic LDO base drive; open drain of an internal N-Channel FETLogic LDO voltage feedback input pin; regulates to 1.2V nominalLow noise signal ground

Negative LDO base drive; open drain of an internal P-Channel FETNegative LDO voltage feedback input pin; regulates to 0.2V nominalPower ground, connected to source of internal N-Channel boost FETBandgap reference output voltage; bypass with a 0.1µF to SGND

VBOOST integrator output; connect capacitor to SGND for PI-mode or connect to VDD for P-mode operation

Boost regulator voltage feedback input pin; regulates to 1.2V nominalEnable pin; High=Enable; Low or floating=DisablePositive supply

Push-pull gate drive of optional fault protection FET; when chip is disabled or when a fault has been detected, this is high

A capacitor connected from this pin to SGND sets the delay time for start-up sequence and sets the fault timeout time

DESCRIPTION

ISL78010

Typical Performance Curves

100

VDD = 9V

80EFFICIENCY (%)

6040200

AVDD = 15V

EFFICIENCY (%)

A= 12V

TA = +25°C, unless otherwise specified.

10080

AVDD

6040200

AVDD = 9V

VDD 0100200IOUT (mA)

300400

0200400IOUT (mA)

600800

FIGURE 1.VBOOST EFFICIENCY AT VIN=3V(PI-MODE)

100

80EFFICIENCY (%)

FIGURE 2.VBOOST EFFICIENCY AT VIN=5V(PI-MODE)

10080EFFICIENCY (%)

6040200

AVDD = 15V

6040200

VDD = 9V

AVDD 0200400IOUT (mA)

600800

IOUT (mA)

FIGURE 3.VBOOST EFFICIENCY AT VIN=3V (P-MODE)FIGURE 4.VBOOST EFFICIENCY AT VIN=5V (P-MODE)

0LOAD REGULATION (%)

LOAD REGULATION (%)

-0.1-0.2-0.3-0.4-0.5-0.6-0.7

100

200IOUT (mA)

300

400

VDD = 12V

AVDD = 15V

A= 9V

0-0.2-0.4-0.6-0.8-1.0

AVDD AVDD AVDD = 9V

0200400IOUT (mA)

600800

FIGURE 5.VBOOST LOAD REGULATION AT VIN=3V(PI-MODE)FIGURE 6.VBOOST LOAD REGULATION AT VIN = 5V (PI-MODE)

ISL78010

Typical Performance Curves

TA = +25°C, unless otherwise specified. (Continued)

LOAD REGULATION (%)

LOAD REGULATION (%)

-0.5-1.0-1.5-2.0-2.5-3.0-3.5-4.0

100

A= 12V

200300IOUT (mA)

400

500

A= 15V

AVDD = 9V

0-1-2-3

AVDD -4-5

AVDD = 15V

200

400IOUT (mA)

600

800

AVDD = 9V

FIGURE 7.VBOOST LOAD REGULATION AT VIN=3V (P-MODE)

0.05LINE REGULATION (%)

FIGURE 8.VBOOST LOAD REGULATION AT VIN=5V (P-MODE)

0LINE REGULATION (%)

-0.5-1.01.5-2.0-2.5

0.040.030.020.010-0.01-0.02

3.0

3.5

4.0

4.5VIN (V)

5.0

5.5

6.0

3.03.54.0

4.5VIN (V)

5.05.56.0

FIGURE 9.VBOOST LINE REGULATION (PI-MODE)FIGURE 10.VBOOST LINE REGULATION (P-MODE)

LOAD REGULATION (%)

-0.1-0.2-0.3-0.4-0.5-0.6

20

40IOUT (mA)

60

80

LOAD REGULATION (%)

0-0.2-0.4-0.6-0.8-1.0-1.2-1.4

20

40

60

80

100

IOUT (mA)

FIGURE 11.VON LOAD REGULATIONFIGURE 12.VOFF LOAD REGULATION

ISL78010

Typical Performance Curves

LOAD REGULATION (%)

-0.2-0.4

-0.6-0.8-1.0-1.2

100

200

300

400

500

600

700

VREFVBOOSTVLOGICVCDLY

TA = +25°C, unless otherwise specified. (Continued)

TIME (10ms/DIV)

IOUT (mA)

FIGURE 13.VLOGIC LOAD REGULATION

FIGURE 14.START-UP SEQUENCE

VBOOSTVLOGICVOFFVON

VBOOST_DELAY

VLOGICVOFFVON

TIME (10ms/DIV)

TIME (10ms/DIV)

FIGURE 15.START-UP SEQUENCE …… 此处隐藏：4854字，全部文档内容请下载后查看。喜欢就下载吧 ……