蛇形机器人说明书 - 图文(8)

http://www.cs.cmu.edu/~biorobotics/projects/modsnake/index.html

[14]Nilsson Martin．Snake robot free climbing[J]．IEEE Control Systems，1998．2：21— 26

[15]A behavior-based arm contoller.Jonathan H Connell, MIT AI Memo 1025,June1988 [16]The Mobile Robotics Lab at the University of Michigan (UM) .The OmniTread serpentine robot ，http://www.engin.umich.edu/research/mrl/00MoRob_6.html [17]How Snakes Walk.http://chabin.laurent.free.fr/snake.htm

附录Ⅰ

26

附录Ⅱ

27

附录Ⅲ

接收控制程序如下，发射程序与之类似，省略之。

/************************************************************************* ;filename :rf.c ;RF :A7105 ;rf crystal :16MHZ ;RF rate :250k

;mcu :STC12C2052AD ;writeby : ;describe :A7105 控制 ;notice :Fdev 固定为 80k

;***********************************************************************/ #include \

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U8 const code Rf_Rate_Tab[7] = {19,9,7,4,3,1,0}; //25k,50k,62.5k,100k,125k,250k,500k // A7105 寄存器默认配置

U8 const code A7105_Default_Par[51] = {

//0x00 register

0x00, // RESET register : not use on config //0x01 register //#if(TEST_MODE) // 0xc2, // direct mode //#else 0x42, // MODE register: FIFO mode //#endif

//0x02 register

0x00, // CALIBRATION register //0x03 register

RF_FIFO_LEN - 1, // FIFO1 register : packet length //0x04 register

0xc0, // FIFO2 register : FIFO pointer margin threshold 16/48bytes(TX/RX) //0x05 register

0x00, // fifo register,not use on config //0x06 register

0x00, // ID data register,not use on config //0x07 register

0x00, // RCOSC1 register 0x00, // RCOSC2 register 0x00, // RCOSC3 register //0x0a register

// 0x02, // CKO register,clk out enable,bit clock 0x00, // CKO disable //0x0b register

0x01, // GPIO1 register :WTR output,enable GPIO1 output 0x09, // GPIO2 register :CD carrier detect,enable GPIO2 output // GPIO1，2按上面设置时，GPIO1保持为高电平， // 发送方发送一帧数据时，GPIO1会由高变低，接收方GPIO2也由高变低 //0x0d register

0x05, // CLOCK register: Crystal oscillator enable bit //0x0e register

0x01, // data rate select 250K

// data rate = system clock / 32*(SDR[7:0] + 1 // 0x04, // data rate = 100k //0x0f register

0x03, // PLL register1, LO channel number select

// channel = 0x14 RF frequency = 2400MHZ + 500K * 20 = 2.410GHZ //0x10 register

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0x9e, // PLL register2,

// DBL = 1, crystal frequency double select

// RRC[1:0] = 00, Fpfd = Fcrystal(16MHZ) * (1 + DBL) /(RRC[1:0] + 1) = 32MHZ

// CHR[3:0] = 0x0F, channel frequency step setting

// channel setp frequency = 0.25 * Fpfd / (CHR[3:0] + 1) = 500KHZ //0x11 register

0x4b, // PLL register3 BIP[7:0] = 75 0x00, // PLL register4 BFP[15:8] = 0 0x00, //0x14 register // 0x06, 0x16, // 0x2b, /2^24 = 187.5KHZ

// 0x20, // 0x21, // 0x22, 0x23, // 0x24, // 0x25, // 0x26, // 0x27, // 0x28, // 0x29, // 0x2a, // 0x2b, // 0x2c, // 0x2d, // 0x2e, // 0x2f, // 0x30, // 0x32, // 0x39, //0x16 register 0x12, //0x17 register

// PLL register5 BFP[7:0] = 0 // TX register1 // frequency deviation power setting = [110] // TX modulation disable // enable tx modulation //0x15 register // Fdev = 187k // TX register2

// Fpfd = 32MHZ,PDV[1:0] = 01,SDR[7:0] = 0000 0001 // Tx rate = Fpfd / (32 * (PDV[1:0]+1) * (SDR[7:0]+1)) = 250kbps

// TX frequency deviation = Fpfd * 127 * 2^FDP[2:0] * (FD[4:0]+1) // Fdev = 15K @FD[2:0] = [110] // Fdev = 31k @FD[2:0] = [110] // Fdev = 46k @FD[2:0] = [110] // Fdev = 62k @FD[2:0] = [110] // Fdev = 80k @FD[2:0] = [110] // Fdev = 93k @FD[2:0] = [110] // Fdev = 108k @FD[2:0] = [110] // Fdev = 124k @FD[2:0] = [110] // Fdev = 139k @FD[2:0] = [110] // Fdev = 155k @FD[2:0] = [110] // Fdev = 170k @FD[2:0] = [110] // Fdev = 186k @FD[2:0] = [110] // Fdev = 200k @FD[2:0] = [110] // Fdev = 217k @FD[2:0] = [110] // Fdev = 232k @FD[2:0] = [110] // Fdev = 248k @FD[2:0] = [110] // Fdev = 263k @FD[2:0] = [110] // Fdev = 294k @FD[2:0] = [110]

// Fdev = 400k @FD[2:0] = [110] // Delay register1

// DPR[2:0] = 0, TDL[1:0] = 2, PDL[2:0] = 2

// TX setting delay = 20*(TDL[1:0]+1)*(DPR[2:0]+1) = 20*3 = 60us // PLL setting delay = 20*(PDL[2:0]+1)*(DPR[2:0]+1) = 20*3 = 60us 30