现代电子技术综合实验报告—简易数字频率计(3)

-- Create Date: 10:32:01 09/15/2011 -- Design Name:

-- Module Name: latch - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: --

-- Dependencies: --

-- Revision:

-- Revision 0.01 - File Created -- Additional Comments: --

----------------------------------------------------------------------------------

---------------------------------------------------------------------------------- library IEEE;

use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM;

--use UNISIM.VComponents.all;

entity latch is

Port ( latchin : in STD_LOGIC; overin : in STD_LOGIC;

numin1 : in STD_LOGIC_VECTOR (3 downto 0); numin2 : in STD_LOGIC_VECTOR (3 downto 0);

现代电子技术综合实验报告—简易数字频率计,基于XILINX的FPGA设计的简易频率计,用ISE仿真,采用VHDL编程,

numin3 : in STD_LOGIC_VECTOR (3 downto 0); numin4 : in STD_LOGIC_VECTOR (3 downto 0); numin5 : in STD_LOGIC_VECTOR (3 downto 0); numin6 : in STD_LOGIC_VECTOR (3 downto 0); overout : out STD_LOGIC;

numout1 : out STD_LOGIC_VECTOR (3 downto 0); numout2 : out STD_LOGIC_VECTOR (3 downto 0); numout3 : out STD_LOGIC_VECTOR (3 downto 0); numout4 : out STD_LOGIC_VECTOR (3 downto 0); numout5 : out STD_LOGIC_VECTOR (3 downto 0); numout6 : out STD_LOGIC_VECTOR (3 downto 0)); end latch;

architecture Behavioral of latch is begin

process(latchin,overin ,numin1,numin2,numin3,numin4,numin5,numin6) begin

if rising_edge(latchin)

then

numout1 <= numin1; numout2 <= numin2; numout3 <= numin3; numout4 <= numin4; numout5 <= numin5; numout6 <= numin6; overout <= overin; end if;

end process; end Behavioral;

显示控制

用频率1KHz的信号实现对六位已经锁存的计数结果的扫描输出

显示控制整体电路如下图：

现代电子技术综合实验报告—简易数字频率计,基于XILINX的FPGA设计的简易频率计,用ISE仿真,采用VHDL编程,

源程序：

---------------------------------------------------------------------------------- -- Company: -- Engineer: --

-- Create Date: 10:39:58 03/24/2011 -- Design Name:

-- Module Name: disp_module - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: --

-- Dependencies: --

-- Revision:

-- Revision 0.01 - File Created -- Additional Comments: --

---------------------------------------------------------------------------------- library IEEE;

use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM;

--use UNISIM.VComponents.all;

现代电子技术综合实验报告—简易数字频率计,基于XILINX的FPGA设计的简易频率计,用ISE仿真,采用VHDL编程,

entity disp_module is

Port ( f1khz : in STD_LOGIC; q_over : in STD_LOGIC;

freq_value0 : in STD_LOGIC_VECTOR (3 downto 0); freq_value1 : in STD_LOGIC_VECTOR (3 downto 0); freq_value2 : in STD_LOGIC_VECTOR (3 downto 0); freq_value3 : in STD_LOGIC_VECTOR (3 downto 0); freq_value4 : in STD_LOGIC_VECTOR (3 downto 0); freq_value5 : in STD_LOGIC_VECTOR (3 downto 0);

se1 : in STD_LOGIC; se10 : in STD_LOGIC; se100 : in STD_LOGIC;

dp1 : in STD_LOGIC; dp2 : in STD_LOGIC; G : out STD_LOGIC;

led : out STD_LOGIC_VECTOR (6 downto 0); sel : out STD_LOGIC_VECTOR (2 downto 0); dp : out STD_LOGIC); end disp_module;

architecture Behavioral of disp_module is

signal sel1: STD_LOGIC_VECTOR (2 downto 0); signal hide1: STD_LOGIC;

signal Freq_out1: STD_LOGIC_VECTOR (3 downto 0);

COMPONENT xsxiaoshudian

Port ( sel : in STD_LOGIC_VECTOR (2 downto 0);

se1 : in STD_LOGIC; se10 : in STD_LOGIC; se100 : in STD_LOGIC; dp : out STD_LOGIC); END COMPONENT; COMPONENT xsjsq

Port ( clk : in STD_LOGIC;

sel : out STD_LOGIC_VECTOR (2 downto 0)); END COMPONENT; COMPONENT xsxydl

Port ( Freq_value0 : in STD_LOGIC_VECTOR (3 downto 0); Freq_value1 : in STD_LOGIC_VECTOR (3 downto 0); Freq_value2 : in STD_LOGIC_VECTOR (3 downto 0); Freq_value3 : in STD_LOGIC_VECTOR (3 downto 0); Freq_value4 : in STD_LOGIC_VECTOR (3 downto 0); Freq_value5 : in STD_LOGIC_VECTOR (3 downto 0);