现代电子技术综合实验报告—简易数字频率计(2)

现代电子技术综合实验报告—简易数字频率计,基于XILINX的FPGA设计的简易频率计,用ISE仿真,采用VHDL编程,

clkout10 : in STD_LOGIC;

clkout100 : in STD_LOGIC; fout : out STD_LOGIC; dp1 : out STD_LOGIC; dp2 : out STD_LOGIC); end gate_sel;

architecture Behavioral of gate_sel is

signal se:STD_LOGIC_VECTOR(2 downto 0):="000"; signal f01,f001:std_logic:='0'; begin

process(se1,se10,se100,clkout1,clkout10,clkout100) begin

se <= se1 & se10 & se100; case se is

when "100" => fout <= clkout1; dp1 <= '1'; dp2 <= '1'; when "010" => fout <= clkout10 ; dp1<= '1'; dp2<= '0'; when "001" => fout <= clkout100 ; dp1<= '0' ; dp2<= '1'; when others => null; end case; end process; end Behavioral;

仿真测试：

门控电路

源程序：

-- Company: -- Engineer: --

-- Create Date: 18:53:38 09/15/2011 -- Design Name:

-- Module Name: gate_control - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description:

----------------------------------------------------------------------------------

现代电子技术综合实验报告—简易数字频率计,基于XILINX的FPGA设计的简易频率计,用ISE仿真,采用VHDL编程,

--

-- Dependencies: --

-- Revision:

-- Revision 0.01 - File Created -- Additional Comments: --

---------------------------------------------------------------------------------- library IEEE;

use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM;

--use UNISIM.VComponents.all;

entity gate_control is

Port ( Bsignal : in STD_LOGIC; Gate : out STD_LOGIC; Reset : out STD_LOGIC; Latch : out STD_LOGIC); end gate_control;

architecture Behavioral of gate_control is signal G1,G2,G3:STD_LOGIC:='0';

signal sel:STD_LOGIC_VECTOR(2 downto 0); begin

process(Bsignal,sel,G1) begin

if rising_edge(Bsignal)

then G1 <= not G1; end if;

if falling_edge(Bsignal) then

G2 <= not G1; end if;

end process; Latch<=G2; Gate<=G1;

现代电子技术综合实验报告—简易数字频率计,基于XILINX的FPGA设计的简易频率计,用ISE仿真,采用VHDL编程,

process (Bsignal,sel,G1,G2) begin

sel<=Bsignal & G1 & G2;

if (sel="001") then G3 <= '1'; else G3 <= '0'; end if;

end process; Reset<=G3; end Behavioral;

仿真测试：

此门控电路在gate为高电平的时候开始计数，latch为高电平的时候锁存，reset为高电平的时候计数器清零。

频率计数器

同步级联

现代电子技术综合实验报告—简易数字频率计,基于XILINX的FPGA设计的简易频率计,用ISE仿真,采用VHDL编程,

异步级联

源程序：

---------------------------------------------------------------------------------- -- Company: -- Engineer: --

-- Create Date: 11:08:36 09/15/2011 -- Design Name:

-- Module Name: counter6 - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: --

-- Dependencies: --

-- Revision:

-- Revision 0.01 - File Created -- Additional Comments: --

---------------------------------------------------------------------------------- library IEEE;

use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM;

--use UNISIM.VComponents.all;

entity counter6 is

Port ( Csignal : in STD_LOGIC; clear : in STD_LOGIC; count_en : in STD_LOGIC;

现代电子技术综合实验报告—简易数字频率计,基于XILINX的FPGA设计的简易频率计,用ISE仿真,采用VHDL编程,

over : out STD_LOGIC;

result1 : out STD_LOGIC_VECTOR (3 downto 0); result2 : out STD_LOGIC_VECTOR (3 downto 0); result3 : out STD_LOGIC_VECTOR (3 downto 0); result4 : out STD_LOGIC_VECTOR (3 downto 0); result5 : out STD_LOGIC_VECTOR (3 downto 0); result6 : out STD_LOGIC_VECTOR (3 downto 0)); end counter6;

architecture Behavioral of counter6 is signal carry_out1:STD_LOGIC:='0'; signal carry_out2:STD_LOGIC:='0'; signal carry_out3:STD_LOGIC:='0'; signal carry_out4:STD_LOGIC:='0'; signal carry_out5:STD_LOGIC:='0'; signal carry_out6:STD_LOGIC:='0'; signal temp:STD_LOGIC:='0'; COMPONENT counter

Port ( rst : in STD_LOGIC; clk : in STD_LOGIC; carry_in : in STD_LOGIC; carry_out : out STD_LOGIC;

count_out : out STD_LOGIC_VECTOR (3 downto 0));

END COMPONENT; BEGIN

c1:counter PORT MAP ( clear, Csignal, count_en,carry_out1,result1) ; c2:counter PORT MAP ( clear, carry_out1, count_en,carry_out2,result2) ; c3:counter PORT MAP ( clear, carry_out2, count_en,carry_out3,result3) ; c4:counter PORT MAP ( clear, carry_out3, count_en,carry_out4,result4) ; c5:counter PORT MAP ( clear, carry_out4, count_en,carry_out5,result5) ;

c6:counter PORT MAP ( clear, carry_out5, count_en,carry_out6,result6) ;

process(carry_out6) begin

if clear = '1' then

over <= '1'; over <= '0';

elsif carry_out6 = '1' then end if;

end process; end Behavioral;

----------------------------------------------------------------------------------

现代电子技术综合实验报告—简易数字频率计,基于XILINX的FPGA设计的简易频率计,用ISE仿真,采用VHDL编程,

-- Company: -- Engineer: --

-- Create Date: 09:26:07 09/15/2011 -- Design Name:

-- Module Name: counter - Behavioral -- Pr …… 此处隐藏：4325字，全部文档内容请下载后查看。喜欢就下载吧 ……