T430HVN01.0 SKD product final spec_v1.3_LBC_20140909(2)

AUO T430HVN01.0 SKD CELL液晶玻璃规格书

T430HVN01.0 Product Specification Rev 1.33. Electrical SpecificationThe T430HVN01.0 Open Cell Unit requires power input which is employed to power the LCD electronics and to drive the TFT array and liquid crystal.3.1 Electrical Characteristics 3.1.1 DC CharacteristicsParameter LCD Power Supply Input Voltage Power Supply Input Current Power Consumption Inrush Current Permissible Ripple of Power Supply Input Voltage Input Differential Voltage Differential Input High Threshold LVDS Interface Voltage Differential Input Low Threshold Voltage Input Common Mode Voltage CMOS Interface Input High Threshold Voltage Input Low Threshold Voltage VDD IDD PC IRUSH VRP 10.8 ----200 +100 12 0.43 5.16 --400 -13.2 0.9 10.8 4 VDD * 5% 600 +300 VDC A Watt A mVpk-pk mVDC mVDC 1 1 2 3 4 4 Symbol Value Min. Typ. Max Unit Note∣VID∣VTHVTL VICM VIH (High) VIL (Low)-300 1.1 2.7 0-1.25 ----100 1.4 3.3 0.6mVDC VDC VDC VDC4 4 5 5© Copyright AU Optronics Corp. 2014 All Rights Reserved.Page 6 / 29

AUO T430HVN01.0 SKD CELL液晶玻璃规格书

T430HVN01.0 Product Specification Rev 1.33.1.2 AC CharacteristicsParameter Symbol Value Min. -500 Fclk -3% 30 Typ. ---Max +500 Fclk +3% 200 Unit NoteInput Channel Pair Skew Margin Receiver Clock : Spread Spectrum Modulation range Receiver Clock : Spread Spectrum Modulation frequency Receiver Data Input Margin Fclk = 85 MHz Fclk = 65 MHz SCL clock frequency Clock Pulse Width Low Clock Pulse Width High Clock Low to Data Output Valid Start Setup Time I2C Interface Start Hold Time Stop Setup Time Data In Setup Time Data In Hold Time SCL/SDA Rise Time SCL/SDA Fall TimetSKEW (CP) Fclk_ss Fssps MHz KHz6 7 7LVDS InterfacetRMG-0.4 -0.5 1.85 0.4 1.76 0.6 0.6 0.6 0.1 0 ----0.4 0.5 350 0.3 0.3ns8fSCL tLOW tHIGH tAA tSTASU tSTAHD tSTOSU tDSU tDHD tR tFkHz us us us us us us us us us us 9© Copyright AU Optronics Corp. 2014 All Rights Reserved.Page 7 / 29

AUO T430HVN01.0 SKD CELL液晶玻璃规格书

T430HVN01.0 Product Specification Rev 1.33.1.3 DRIVER CHARACTERISTICSItem Symbol DST Min Max 100 Unit [ condition Note℃] Note : Any point on the driver surface must be less than 100℃ under any conditions.Driver Surface Temperature3.1.4 TCON CharacteristicsItem Symbol TST Min Max 85 Unit [ condition Note℃] Note : Any point on the TCON surface must be less than 85℃ under any conditions.TCON Surface Temperature Note : 1. Test Condition: (1) VDD = 12.0V (2) Frame rate = 60Hz (3) Fclk= Max freq. (4) Temperature = 25 (5) Typ. Input current : White Pattern Max. Input current: Heavy loading pattern defined by AUO℃2.Measurement condition : Rising time = 400us90% VDDGND10% 400 µs3. Test Condition: (1) The measure point of VRP is in LCM side after connecting the System Board and LCM. (2) Under Max. Input current spec. condition. 4. VICM = 1.25VLVDS V IC M LVDS + V TH |V ID | V TLGND|V ID |0V|V ID |© Copyright AU Optronics Corp. 2014 All Rights Reserved.Page 8 / 29

AUO T430HVN01.0 SKD CELL液晶玻璃规格书

T430HVN01.0 Product Specification Rev 1.35. The measure points of VIH and VIL are in LCM side after connecting the System Board and LCM. 6. Input Channel Pair Skew Margin.Note: x = 0, 1, 2, 3, 4 7. LVDS Receiver Clock SSCG (Spread spectrum clock generator) is defined as below figures.1/FSS Fclk_ Fclk_ss( ss(max) max)FclkFclk_ Fclk_ss( ss(min) min)8. Receiver Data Input Margin Parameter Input Clock Frequency Input Data Position0 Input Data Position1 Input Data Position2 Input Data Position3 Input Data Position4 Input Data Position5 Input Data Position6 Symbol Fclk tRIP1 tRIP0 tRIP6 tRIP5 tRIP4 tRIP3 tRIP2 Rating Min Fclk (min) -|tRMG| T/7-|tRMG| 2T/7-|tRMG| 3T/7-|tRMG| 4T/7-|tRMG| 5T/7-|tRMG| 6T/7-|tRMG| Type -0 T/7 2T/7 3T/7 4T/7 5T/7 6T/7 Max Fclk (max) |tRMG| T/7+|tRMG| 2T/7+|tRMG| 3T/7+|tRMG| 4T/7+|tRMG| 5T/7+|tRMG| 6T/7+|tRMG| Unit MHz ns ns ns ns ns ns ns Note T=1/Fclk© Copyright AU Optronics Corp. 2014 All Rights Reserved.Page 9 / 29

AUO T430HVN01.0 SKD CELL液晶玻璃规格书

T430HVN01.0 Product Specification Rev 1.3tRIP2 tRIP3 tRIP4 tRIP5 tRIP6 tRIP0 tRIP1 LVDS-Rx Input Data LVDS-Rx Input Clock Rx3 Rx2 Rx1 Rx0 Rx6 Rx5 Rx4 Rx3 Rx2 Rx1 Rx0 Rx6Vdiff = 0V 1/Fclk=T9. I2C Read/Write TimingSTART STOPSDA70%tR tF30% 30%70%INtSTASUtSTAHDtDSUtDHDtSTOSUSCL tAA SDA OuttHIGHtLOW© Copyright AU Optronics Corp. 2014 All Rights Reserved.Page 10 / 29

AUO T430HVN01.0 SKD CELL液晶玻璃规格书

T430HVN01.0 Product Specification Rev 1.33.2 Interface Connections 3.2.1 T-Con Board Pin MapLCD connector: 196395-60041-3 (P-TWO, LVDS connector，母頭) PIN 1 2 Symbol N.C. SCL Description No connection (for AUO test only. Do not connect) EEPROM Serial Clock EEPROM Write Protection 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 WP SDA N.C. N.C. LVDS_SEL N.C. N.C. N.C. GND CH1_0CH1_0+ CH1_1CH1_1+ CH1_2CH1_2+ GND CH1_CLKCH1_CLK+ GND CH1_3CH1_3+ N.C. High(3.3V) for Writable, Low(GND) for Protection EEPROM Serial Data No connection (for AUO test only. Do not connect) No connection (for AUO test only. Do not connect) Open/High(3.3V) for NS, Low(GND) for JEIDA No connection (for AUO test only. Do not connect) No connection (for AUO test only. Do not connect) No connection (for AUO test only. Do not connect) Ground LVDS Channel 1, Signal 0LVDS Channel 1, Signal 0+ LVDS Channel 1, Signal 1LVDS Channel 1, Signal 1+ LVDS Channel 1, Signal 2LVDS Channel 1, Signal 2+ Ground LVDS Channel 1, Clock LVDS Channel 1, Clock + Ground LVDS Channel 1, Signal 3LVDS Channel 1, Signal 3+ No connection (for AUO test 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 CH2_0+ CH2_1CH2_1+ CH2_2CH2_2+ GND CH2_CLKCH2_CLK+ GND CH2_3CH2_3+ N.C. N.C. N.C. N.C. GND GND GND N.C. VDD VDD LVDS Channel 2, Signal 0+ LVDS Channel 2, Signal 1LVDS Channel 2, Signal 1+ LVDS Channel 2, Signal 2LVDS Channel 2, Signal 2+ Ground LVDS Channel 2, Clock LVDS Channel 2, Clock + Ground LVDS Channel 2, …… 此处隐藏：7059字，全部文档内容请下载后查看。喜欢就下载吧 ……