A 201.4 GOPS 496 mW Real-Time Multi-Object Recognition Proce(4)

A 201.4 GOPS real-time multi-object recognitionprocessor is presented with a three-stage pipelined architecture.Visual perception based multi-object recognition algorithm isapplied to give multiple attentions to multiple objects in the inputimage. For human-like multi-object perception, a neural perceptionengine is proposed with biologically inspired neural networksand fuzzy logic circ

40IEEEJOURNALOFSOLID-STATECIRCUITS,VOL.45,NO.1,JANUARY

2010

Fig.10.Blockdiagramofdecisionprocessor.

V.MULTI-CASTINGNETWORK-ON-CHIP

AsthenumberofIPblocksincreasestoaddresscomputingrequirementsofrecentmultimediaprocessing,conventionalsharedmediumbasedcommunicationrevealsitslimitationstohandlesimultaneousdatatransactionsamongmultipleIPblocks.Asanalternative,anetwork-on-chip(NoC)ishigh-lightedassuitablecommunicationarchitectureinmulti-coreerainspiteofitshighimplementationcostscomparedwithconventionalbus,becauseitprovidessuf cientbandwidthtomultipleIPblocksandhasgoodscalabilitywithdistributedrouterswitches[15]–[17].Inthisprocessor,amulti-castingnetwork-on-chip(MC-NoC)isproposedtointegrateallof21IPblocks.Tocopewiththeprocessor’sapplication-drivendatatransactionssuchas1-to-Nbroad/multi-castingandinter-pro-cessordatacommunications,theMC-NoChasanewcombinedarchitectureandsupportsamulti-castingcapability.

Fig.11showstheproposedMC-NoCarchitecturethatcon-sistsofa

910systemnetworkandfour

77SPUcluster(SPC)networks.The16SPUsareconnectedtothesystemnetworkthroughthefourSPCnetworkswhiletheNPE,STM,DP,andtwoexternalinterfacesaredirectlyconnectedtothesystemnetwork.Itadoptsahierarchicalstartopology[15]asabasictopologyforlowlatencydatacommunications,andthen,supplementsaringtopologytotheSPCnetworksforhigh-speedinter-SPUdatatransactions.Theadditionalnetworklinksforthecombinedtopologyprovides25.6GB/saggregatedbandwidthbetweentheSPCnetworksandallowseachSPUtoaccesstheotherSPUsinneighborclustersintwoswitchhops.Inoverall,topology-combinedMC-NoCprovidesa118.4GB/stotalbandwidthwiththeswitchhoplatencyoflessthan3.TheproposedMC-NoCadoptsawormholeroutingprotocolwhosepacketiscomposedofheader,address,anddata owcontrolunits(FLITs).EachFLITconsistsof2-bitcontrolsignalsand34-bitdatasignalsincluding2-bitFLITtypeindicator.TheheaderFLITcontainsallinformationfortheentirepackettransmissionsuchas4-bitburstlengthforburstdata

transaction

Fig.11.Proposedmulti-castingNoCarchitecture.

uptoeightFLITsand2-bitprioritylevelforquality-of-service.The16-bitsourcede nedroutinginformation(RI)allowsfourswitchtraversalsfornormalpacketsandmulti-castingtoarbi-trarySPUsformulti-castingpackets.Incaseofmulti-castingpackets,eachbitof16-bitRIindicateseachdestinationSPU.IntheMC-NoC,multi-castingfromtheNPE/STMtothe16SPUsissupportedtoaccelerate1-to-Ndatatransactionssuchasprogramkerneldistributionandimagedatadownload.Tothisend,eachnetworkswitchisdesignedtohavemulti-castingability.Fig.12showsafour-stagepipelinedmulti-castingcrossbarswitchanditsmulti-castingport.Itconsistsofinputports,arbiters,muxbasedcrossbarfabric,andoutputports.At rst,theincomingFLITsarebufferedatthe8-depthFIFOqueuethatcontainsthesynchronizationinterface[18]forheterogeneousclockdomainconversion.Then,eachactiveinputportsendsarequestsignaltoitsdestinationarbitertogetagrantsignaltotraversethecrossbarfabric.Forschedulingofgrantsignals,thearbitersperformasimpleround-robinsched-ulingaccordingtotheprioritylevels.Incaseofmulti-casting

A 201.4 GOPS real-time multi-object recognitionprocessor is presented with a three-stage pipelined architecture.Visual perception based multi-object recognition algorithm isapplied to give multiple attentions to multiple objects in the inputimage. For human-like multi-object perception, a neural perceptionengine is proposed with biologically inspired neural networksand fuzzy logic circ

KIMetal.:A201.4GOPS496mWREAL-TIMEMULTI-OBJECTRECOGNITIONPROCESSORWITHBIO-INSPIREDNEURALPERCEPTIONENGINE

41

Fig.12.Four-stagepipelinedmulti-castingswitchanditsmulti-castingport.

packet,amulti-castinginputportsendsmultiplerequeststoalldestinationarbitersatthesametimeandwaitsuntilallgrantsignalsarereturned.Tothisend,inthemulti-castinginputport,amulti-portrequesterdecodesthe16-bitRIandgeneratescorrespondingrequestsignalsandagrantcheckerholdsthemulti-castingpacketuntiltheregisteredrequestsignalsareequaltothereceivedgrantsignals.Afterallgrantsaregathered,multi-castingisperformedusingtheexistingbroad-castedwiresofcrossbarfabricwithoutanyadditionalwires.Avari-ablestrengthdriverisspeciallyemployedforthemulti-castingporttoprovidesuf cientdrivingstrengthformulti-casting.Asaresult,theMC-NoC’smulti-castingcapabilityacceleratestheprogramkerneldistributionandimagedatadownloadtaskofthetargetobjectrecognitionby

6.56and

1.22,respectively.

VI.LOW-POWERTECHNIQUES

Toreducepowerconsumptionduringtheobjectrecognitionprocessing,chip-levelpowermanagementisperformedbytheSTM.Fig.13showspowermanagementarchitectureoftheproposedprocessoranditsworkload-awaredynamicpowermanagement.Inthechip,powerdomainofthe16SPUsisdividedintofourdomainsandeachofthemisindependentlycontrolledbytheSTM.Tocontrolthepowerdomains,off-chippowergatingmethod[19]isemployedforlowcostimplemen-tation.Anexternalregulatorwithenablesignalisemployedforeachofthepowerdomains.Therestpartsofthechip,theNPE,STM,DPandNoC,areplacedinalways-ondomain.Foref cientpowergatingofthechip,workload-awarepowergating(WAPG)isadoptedwithworkload-awaretasksched-uling(WATS).WhentheSTMmeasurestheworkloadoftheSPUsbasedonthenumberofROIgrid-tilesanddeterminesthenumberofactivatingSPUs,italsodeterminesthenumberofactivatedpowerdomainsinproportionaltotheworkloadamount,asshowninthe owchartofFig.13.Afterthat,theSTMsendsrequestsignalstoexternalregulatorstogateunusedpowerdomainsofSPUsbeforeitassignstheROIgrid-tiletaskstotheSPUs.Consideringafewhundreds

ofssettlingtimeofexternalregulators,therequestsforpowergatingoccuronlyonceperframe.BytheWAPG,thenumberofactivated …… 此处隐藏：6327字，全部文档内容请下载后查看。喜欢就下载吧 ……