-操作系统精髓与设计原理(第五版)+课后题答案1(2)

-操作系统精髓与设计原理(第五版)+课后题答案1

CHAPTER 7

MEMORY MANAGEMENT

Review Questions

7.1 Relocation, protection, sharing, logical organization, physical

organization.

7.7 A logical address is a reference to a memory location independent of the

current assignment of data to memory; a translation must be made to a physical address before the memory access can be achieved. A relative address is a particular example of logical address, in which the address is expressed as a location relative to some known point, usually the

beginning of the program. A physical address, or absolute address, is an actual location in main memory.

Problems

7.6 a. The 40 M block fits into the second hole, with a starting address of 80M.

The 20M block fits into the first hole, with a starting address of 20M. The 10M block is placed at location 120M.

40M40M60M40M30M40M40M

b. The three starting addresses are 230M, 20M, and 160M, for the 40M, 20M, and 10M blocks, respectively.

40M60M60M40M30M40M40M

c. The three starting addresses are 80M, 120M, and 160M, for the 40M, 20M, and 10M blocks, respectively.

-操作系统精髓与设计原理(第五版)+课后题答案1

7.12 a. The number of bytes in the logical address space is (216 pages) (210

bytes/page) = 226 bytes. Therefore, 26 bits are required for the logical address.

b. A frame is the same size as a page, 210 bytes.

c. The number of frames in main memory is (232 bytes of main memory)/(210 bytes/frame) = 222 frames. So 22 bits is needed to

specify the frame.

d. There is one entry for each page in the logical address space. Therefore there are 216 entries.

e. In addition to the valid/invalid bit, 22 bits are needed to specify the frame location in main memory, for a total of 23 bits.

40M40M60M40M30M40M40M

d. The three starting addresses are 80M, 230M, and 360M, for the 40M, 20M, and 10M blocks, respectively.

-操作系统精髓与设计原理(第五版)+课后题答案1

CHAPTER 8 VIRTUAL MEMORY

Review Questions

8.1 Simple paging: all the pages of a process must be in main memory for

process to run, unless overlays are used. Virtual memory paging: not all pages of a process need be in main memory frames for the process to run.; pages may be read in as needed

8.2 A phenomenon in virtual memory schemes, in which the processor

spends most of its time swapping pieces rather than executing instructions.

Problems

8.1 a. Split binary address into virtual page number and offset; use VPN as

index into page table; extract page frame number; concatenate offset to get physical memory address

b. (i) 1052 = 1024 + 28 maps to VPN 1 in PFN 7, (7 1024+28 = 7196) (ii) 2221 = 2 1024 + 173 maps to VPN 2, page fault (iii) 5499 = 5 1024 + 379 maps to VPN 5 in PFN 0, (0 1024+379 =

379)

8.4 a. PFN 3 since loaded longest ago at time 20 b. PFN 1 since referenced longest ago at time 160 c. Clear R in PFN 3 (oldest loaded), clear R in PFN 2 (next oldest

loaded), victim PFN is 0 since R=0

d. Replace the page in PFN 3 since VPN 3 (in PFN 3) is used furthest in

the future

-操作系统精髓与设计原理(第五版)+课后题答案1

3 0 2 1

* 4 4 3 0 2

0 0 4 3

0 0 4 3

0 0 4

* 2 2 0

* 4 4 2 0

2 2 4 0

* 1 1 2 4

* 0 0 1 2 4

* 3 3 0 1 2

2 2

VPN of pages in memory in LRU order

-操作系统精髓与设计原理(第五版)+课后题答案1

CHAPTER 9 UNIPROCESSOR SCHEDULING

Review Questions

9.1 Long-term scheduling: The decision to add to the pool of processes to be

executed. Medium-term scheduling: The decision to add to the number of processes that are partially or fully in main memory. Short-term

scheduling: The decision as to which available process will be executed by the processor

9.3 Turnaround time is the total time that a request spends in the system

(waiting time plus service time. Response time is the elapsed time

between the submission of a request until the response begins to appear as output.

Problems

9.1 Each square represents one time unit; the number in the square refers to

the currently-running process.

FCFS

RR, q = 1 RR, q = 4 SPN SRT HRRN Feedback, q = 1 Feedback, q = 2i

-操作系统精髓与设计原理(第五版)+课后题答案1

FCFS RR q = 1

RR q = 4

SPN SRT HRRN FB q = 1

FB q = 2i

Ta Ts Tf Tr Tr/Ts Tf Tr Tr/Ts Tf Tr Tr/Ts Tf Tr Tr/Ts Tf Tr Tr/Ts Tf Tr Tr/Ts Tf Tr Tr/Ts Tf Tr Tr/Ts

A 0 3 3 3.00 1.00 6.00 6.00 2.00 3.00 3.00 1.00 3.00 3.00 1.00 3.00 3.00 1.00 3.00 3.00 1.00 7.00 7.00 2.33 4.00 4.00 1.33

B 1 5 8 7.00 1.40 11.00 10.00 2.00 10.00 9.00 1.80 10.00 9.00 1.80 10.00 9.00 1.80 8.00 7.00 1.40 11.00 10.00 2.00 10.00 9.00 1.80

C 3 2 10 7.00 3.50 8.00 5.00 2.50 9.00 6.00 3.00 5.00 2.00 1.00 5.00 2.00 1.00 10.00 7.00 3.50 6.00 3.00 1.50 8.00 5.00 2.50

D 9 5 15 6.00 1.20 18.00 9.00 1.80 19.00 10.00 2.00 15.00 6.00 1.20 15.00 6.00 1.20 15.00 6.00 1.20 18.00 9.00 1.80 18.00 9.00 1.80

E 12 5 20 8.00 1.60 20.00 8.00 1.60 20.00 8.00 1.60 20.00 8.00 1.60 20.00 8.00 1.60 20.00 8.00 1.60 20.00 8.00 1.60 20.00 8.00 1.60

6.20 1.74 7.60 1.98 7.20 1.88 5.60 1.32 5.60 1.32 6.20 1.74 7.40 1.85 7.00 1.81

-操作系统精髓与设计原理(第五版)+课后题答案1

9.16 a. Sequence with which processes will get 1 min of processor time:

1 2 3 4 5 Elapsed time A B C D E 5 A B C D E 10 A B C D E 15 A B D E 19 A B D E 23 A B D E 27 A B E 30 A B E 33 A B E 36 A E 38 A E 40 A E 42 A 43 A 44 A 45

The turnaround time for each process:

A = 45 min, B = 35 min, C = 13 min, D = 26 min, E = 42 min

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