Equalization and Clock and Data Recovery Techniques for 10-G(4)

2006Fig.17.XORandV/Icircuit.

Fig.18.Diephotographofadaptiveequalizer.

theswingcontrollooptoconverge.Thus,inthisdesign,theswingcontrolloopisthefastest,andtheboostcontrolloop,theslowest.

ThemergingoftheequalizerandtheCDRsavesabout19mWinpowerdissipation.Furthermore,itobviatesseveralinductorsthatwouldotherwisebenecessaryintheslicer.

Theoverallperformanceoftheequalizer/CDRcascadede-pendsontheresidualISI,additivenoise,andclockjitter.Itisthereforenecessarytoquantifythetrade-offsamongthesepa-rameterssothatareasonablejitterbudgetcanbeallocatedtoeachstage.Aframeworkfortheanalysisoftheseeffectsispro-posedinAppendixII.B.CDRCircuit

Thisworkemploysafull-rateCDRcircuitconsistingofanAlexanderphasedetector(PD)[16]andanvoltage-con-trolledoscillator(VCO)(Fig.15).Whileoperatingasabang-bangcircuitandexhibitingahighgain,theAlexanderPDpro-ducesnooutputintheabsenceofdatatransitions,thusleaving

undisturbed.ThehighgainofthePDobviatesachargepumpandpermitstheuseofasimplevoltage-to-current(/)convertertodrivetheloop?lter.NotethatnodesXandYneednotprovideahighbandwidthasonlytheiraveragevoltagesaresensedbythe/converter—animportantadvantageofthisre-alizationoverthoseusingchargepumps.

Thespeed,jitter,anddrivingcapabilityrequiredoftheoscil-latorpointtotheuseofan

implementation.Fig.16depictstheVCOanditsbuffer.Resistor

setsthecorecommon-modeIEEEJOURNALOFSOLID-STATECIRCUITS,VOL.42,NO.9,SEPTEMBER2007

voltagetoapproximately

,maximizingthecapacitancerangeoftheMOSvaractorsandhencethetuningrangeoftheos-cillator.ThebufferisolatesthecorefromthelargecapacitancesassociatedwiththePDdevicesandinterconnectswhilesup-pressingthedatatransitionsthatwouldotherwisecouplefromthePD?ip-?opstotheVCOcore.

TheVCOphasenoiseisdominatedbythemodulationofthevaractorcapacitancesduetothenoisecurrentof.Inthisde-sign,thesimulatedphasenoiseofthefree-runningVCOaspre-dictedbySpectreRFisapproximatelyequalto106dBc/Hzat1-MHzoffset.

TheXORgatesusedinthePDofFig.15mustexhibitsym-metrywithrespecttotheirtwoinputsandoperatewithalowsupplyvoltage.ShowninFig.17alongwiththe/converter,

theXORgateisamodi?edversionofthatin[17].Here

–formtheXORcoreandcopiestheaverageoutputcurrent

into

.Toallowlow-voltageoperation,thedrainvoltageofisraisedbyaboveitsgatevoltage,thussavingonethresholdintheheadroom.Thereferencevoltageisapproximatelyequaltothecommon-modelevelofAandB.The/convertercopiestheaverageoutputcurrentoftheXOR,providingnearlyrail-to-railswingsfortheoscillatorcon-trolline.SensingtheaveragevoltageproducedbytheXOR,the/converterremainsfreefromadeadzone.

VI.EXPERIMENTALRESULTS

ThissectionpresentsexperimentalresultsforthetwocircuitsdescribedinSectionsIVandV.Botharefabricatedin0.13-mCMOStechnology.A.AdaptiveEqualizerI

Fig.18showsaphotographofthedie,whichmeasures0.45mm0.36mm.Thecircuithasbeentestedonahigh-speedprobestationwhilesensing10-Gb/sdatathathastraveledonanFR4board.Thepseudorandombitsequencefollowsa21pattern.Fig.19showstheequalizerinputandoutputwaveformsat10Gb/sfor30-inand6-indifferentialtracesontheFR4boardwithoutanyexternalchangesinthebiasorothercircuitconditions.Inthissetup,the30-inFR4tracehasalossof21dBat5GHz.Theresultsshowthatthehigh-frequencyadaptationloopaccommodatesvaryinglossconditions.Tochecktheoperationofthelow-frequencyadaptationloop,thepatterngeneratoroutputswingwasvariedfrom520–700mVandsimilarresultswereobtained.Notethatthepatterngenerator

GONDIANDRAZAVI:EQUALIZATIONANDCLOCKANDDATARECOVERYTECHNIQUESFOR10-GB/SCMOSSERIAL-LINKRECEIVERS2007

Fig.19.Measuredresultsbeforeandafterequalizationat10Gb/sforFR4traces,(horizontalscale:20ps/div.):(a)beforeequalizationfor30-inFR4(verticalscale:100mV/div.),(b)afterequalizationfor30-inFR4(verticalscale:100mV/div.),(c)afterequalizationfor6-inFR4(verticalscale:100mV/div.).

theequalizer.Thecircuitconsumes133mW,ofwhich41mWisdissipatedintheequalizerand92mWintheCDR.

Fig.23(a)showstherecoveredclockspectrumfora24-inFR4at10Gb/s,displayingaphasenoiseof109dBc/Hzat1-MHzoffset.ThejitterhistograminFig.23(b)suggestsanrmsjitterof2.22ps.TheVCOprovidesatuningrangefrom8.9GHzto11.6GHz.

VII.CONCLUSION

ThehighlossoflongtracesonFR4boardscanbecompen-satedthroughtheuseofequalizationtechniquessuchaspas-sivepeakingnetworks,reversescaling,andcapacitivedegener-ation.Toadapttothelinelength,equalizersmustincorporatebothboostandswingcontrolwhileguaranteeingsmooth,con-?ict-freeconvergence.Finally,theequalizationandCDRfunc-tionscanbemergedtoeliminateslicers.Thisworkhasdemon-stratedtheseconceptsforadatarateof10Gb/sandtracelengthsof24inchesin0.13-mCMOStechnology.

APPENDIXILINEMODELING

Fig.24(a)plotsthelosspro?leofadifferential30-inmicrostriplineonanFR4board.Designedforadifferentialcharacteristicimpedanceof100,thetwotraceshaveawidthof6milandaspacingof12mil.(Thispro?leisobtainedbysimulationofthestructureinSONNET.)Theskineffectand

anddependencies,dielectriclossexhibitapproximately

respectively,andthelosspro?lecanberepresentedas

(5)

whereanddependonthetraceandboardproperties,re-spectively,anddenotesthetracelength.Thus,skineffectisdominantatlowerfrequenciesanddielectricloss,athigherfre-quencies.Inthisexample,skineffectlossbecomesequaltodi-electriclossatapproximately2.5GHz.Thestrongfrequencydependenceofthelossesinthemicrostripmakesitdif?culttousethestandardtransmissionlinemodel[Fig.24(b)],wherethe

andtheparallelconductanceremaincon-seriesresistance

stantwithfrequency.

Whilebroadbandmodelshavebeendevelopedforskineffect[18],anaccuratemodelisnotavailablefordielectricloss.Itis

Fig.20.Diephotographofmergedadaptiveequalizer/CDR.

itselfsuffersfromapeak-to-peakjitterof15ps.Thecircuit(excludingtheoutputbuffer)consumes25mWfroma1.2-Vsupply.

ThedoubletracevisibleinFig.19(c)fora6-inlineresultsfromapproximately2dBofrippleinthecascadefrequencyre-sponseoftheFR4boardandtheequalizer.Con?rmedbysim-ulations,thisripplepossiblyarisesfromtheimperfectmatchbetweent …… 此处隐藏：6378字，全部文档内容请下载后查看。喜欢就下载吧 ……