Equalization and Clock and Data Recovery Techniques for 10-G(3)

2004IEEEJOURNALOFSOLID-STATECIRCUITS,VOL.42,NO.9,SEPTEMBER2007

Fig.9.Proposedadaptiveequalizerarchitecture.

Fig.10.Spectrumbeforeandafterslicerwithswingmismatch.

Fig.11.Simulateddynamicsoftheswingandboostcontrolloops.

differencebetweenhigh-frequencycontentsofthedatabeforeandafterslicing[2],[13],[14].Notethattheslicergeneratesa

spectrum.Ifoperatingrandombinarysequencehavinga

optimally,theequalizermustdothesame.

Theadaptationrequiresthattheequalizernotslice(hard-limit)thedata.Otherwise,theinputandoutputofthe?nalslicercarrysimilarspectra,andtheerrorintheadaptationloopap-proacheszeroevenwithincompleteequalization.Thisissueinturnnecessitatesadequatelinearityintheequalizerpath,8leadingtotwoimportanteffects:1)theequalizeroutputswingis

8A

variable-gainampli?ercanprecedetheequalizertoensurelinearity.

afunctionofthetransmittedsignallevelandotherparametersinthesignalpath,whereasthesliceroutputisnot;and2)theequalizercircuitryisfundamentallydifferentfromthatintheslicer.Forexample,thedifferentialpairsintheequalizermaynotexperiencecompleteswitchingwhereasthoseintheslicermust.

Thus,asillustratedinFig.10,theadaptationmaysettlesuchthatthesignalsatAandBexhibitequalhighfrequencyener-gies(betweenand)whileAisverypoorlyequalized.Theabovedif?cultycanbealleviatedbyaddingaloopforlow-fre-quencyadaptationtomaintainequalswingsatAandB[15].In[15],however,theswingsintheequalizerpathareadjusted,po-tentiallylimitingthetuningrangeandinterferingwiththemainadaptationloop.TheapproachintroducedinthisworkisshowninFig.9,wheretheinputandoutputswingsoftheslicerarecomparedafterrecti?cation,andtheresultingerrorisusedtoadjustthesliceroutputswingratherthantheequalizeroutputswing.Theswingiscontrolledbyadjustingthetailcurrentofalimitingdifferentialpairintheslicer.Theslicerthereforegen-eratesswingsthatmatchtheequalizeroutputswings,allowingnearlycompleteoverlapofspectraatAandBafterequalization.Unlikeimplementationsthatprecedetherecti?erswithhigh-pass?lters(HPFs)[13]–[15],thisdesignemploysbandpass?l-]aroundters(BPFs)tomeasuretheenergyinaband[

5GHz.Thisisbecausethegainpeakingoccursinthevicinityofthisfrequencyandmustbecontrolledaccurately.

GONDIANDRAZAVI:EQUALIZATIONANDCLOCKANDDATARECOVERYTECHNIQUESFOR10-GB/SCMOSSERIAL-LINKRECEIVERS2005

Fig.12.Responseoftheadaptiveequalizertoa25%mismatchintheline.(a)Frequencyresponse.(b)Eyediagram.

Fig.13.Proposedmergedadaptiveequalizer/CDRarchitecture.

ThetwodynamicfeedbackloopsinthearchitectureofFig.9canpotentially“?ght”eachother,thusfailingtoconvergetoap-propriatesettings.Suchacon?ictisavoidedbychoosingsub-stantiallydifferenttimeconstantsforthetwoloops,namely,65nsforswingcontroland105nsforboostcontrol.Fig.11depictsthesimulateddynamicsofthetwoloopsastheysettletotheir?nalvaluesforworst-caseinitialconditions.(Thissim-ulationisperformedonthetransistor-levelimplementationofthecircuit.)

Apossiblepointofconcernisthesensitivityoftheproposedadaptiveequalizertomismatchesinthetransmissionline.Fig.12showstheresponseoftheadaptiveequalizerfora25%mismatchinthetransmissionlineat3.4GHz.Asexpected,thereisonlyagradualdegradationintheeyecomparedtothetransmissionlinewithminimalmismatch[Fig.5(b)].Thisdesignmaybefollowedbyamulti-tapdecision-feedbackequalizertoremovetheresultingISI.

V.MERGEDADAPTIVEEQUALIZER/CDRCIRCUIT

Inbroadbandreceivers,theequalizeristypicallyfollowedbyaCDRcircuit.ThetwofunctionscansimplybecascadedbutwerecognizethattheretimeddataproducedbytheCDRcircuitexhibitsthepropertiesofaslicedwaveform,obviatingtheneedforanexplicitslicer.Sinceslicerstypicallyconsumeseveralinductorsandconsiderablepowertoachievetherequiredbandwidthandgain,theconsolidationofequalizerandCDRcircuitscanyieldsavingsinareaandpowerdissipation.

Fig.14.Simulateddynamicsof(a)boostandswingcontrolsignals,and(b)thecontrolvoltageoftheVCOintheCDRloop.

Fig.15.CDRarchitecture.

Fig.16.VCOandbuffercircuit.

A.Architecture

ShowninFig.13isthearchitectureofthemergedequal-izer/CDRcircuit[12].Theretimeddata,

,providesbothlow-frequencyandhigh-frequencyinformationforadjustingtheboostandswingcontrols.Theswingadjustcircuitisrealizedasasingledifferentialpairwhilethe?lterandtheenergycompar-isonmechanismsaresimilartothoseinFigs.8and9,respec-tively.

ThearchitectureinFig.13entailsastart-upissue.Withhighintersymbolinterference(e.g.,fora24-intrace),iftheequalizerbeginswithminimumboost,theneachdataedgeappliedtotheCDRspansseveralbitperiods,thusprohibitingproperphase-lock.Thearchitecturecontainsthreefeedbackloopswhosetimeconstantsmustbechosencarefullytoensureconvergence.Fig.14showsthedynamicsofthethreeloopsastheyreachsteadystate.OnlywithproperphaselockcantheCDRprovidetheretimeddatatothefeedbackloop;hence,theCDRloopmustsettlebeforetheboostcontrolloop.Notethattheboostcontrolloopisinitiallyreset,providingmaximumpeakingandenablingtheCDRtolock.Also,evenwithoutphase-lock,theretimeddatafromtheCDRissuf?cientfor …… 此处隐藏：2804字，全部文档内容请下载后查看。喜欢就下载吧 ……