Equalization and Clock and Data Recovery Techniques for 10-G(2)

of10dBat10GHztranslates450fF.Ontheotherhand,an

toatotalinputcapacitanceof213fF.AllowingforESDand

fF.3Also,fF.padcapacitance,weassume

.Thus,

Inthiswork,ascalingfactorof1.3ischosentoachieveanimprovementof22%inspeed.Fig.5showsthesimulatedout-putsoftheequalizerforscaledandunscaleddesigns.4Theeyeopeningincreasesbyapproximatelythesamefactor.5

NotethattheuseofmonolithicT-coils[10]cangreatlyin-creasethetolerableinputcapacitanceandhenceprovideaddi-tionalbandwidthimprovementwithreversescaling.

III.EQUALIZERFILTERDESIGN

Inthissection,thepeakingtechniquespresentedinSectionIIIareusedtodesignequalizer?lters.Thesedesignsalsoincorpo-rateadaptiveboostingsoastoallowdifferenttracelengths.A.EqualizerFilterI

ShowninFig.6,the?rstequalizer[9]interspersesthreepeakingstageswithtwogainstagestoprovideaboostfactorofabout22dBat5GHzwhileexhibitingalow-frequencylossoflessthan3dB.6Thedesignexploitsthereversescaling

3Forthesakeofsimplicity,thesecalculationsdonotincludetheuseofpassive

Fig.7.Tuningbehaviorof?ve-stagecascade.

peakingatthefrontend.

4ThedetailsofthiscircuitareshowninFig.6.

designsincorporateotherbroadbandtechniquesaswell(SectionIII).

6Thetwogainstagespartiallycompensatethelossofthepeakingstages,pro-vidinganoutputswingofapproximately1V.

5These

techniquedescribedinSectionIIbutwithslightvariationinthevalueoffromonestagetothenexttoallowoptimizationforhigh-frequencypeakingandlow-frequencyloss.

AsmentionedinSectionII,simpleresistively-loadeddiffer-entialpairscannotyieldtherequiredbandwidth.Thus,induc-tivepeakingandnegativeMillercapacitances[11]havebeenaddedtoimprovethespeedwithoutsacri?cingthevoltagehead-room.Tosavearea,onlythreeofthestagesincorporateinduc-tivepeaking.

Thepeakingstagesintheequalizerpathemployavariable

anddegenerationresistancealongwithMOSvaractors

toprovideawideboostrange.Asthecontrolvoltagerises,theon-resistanceoffallsandsodoesthecapacitanceofand,raisingthemagnitudeofthezero.Notethatthesimul-taneouschangeoftheresistanceandcapacitancegreatlysimpli-?estheadaptationloop(SectionIV).Fig.7illustratesthesim-ulatedtuningbehaviorofthecascadeasthecontrolvoltageissweptfrom0.1Vto1.1V.

AsindicatedinFig.6,thecascadeemployscapacitivecouplingbetweensomestagestoisolatecommon-mode

GONDIANDRAZAVI:EQUALIZATIONANDCLOCKANDDATARECOVERYTECHNIQUESFOR10-GB/SCMOSSERIAL-LINKRECEIVERS2003

Fig.8.Equalizer?lterIIarchitecture.

(CM)levels.Thismitigatesthevoltageheadroomissueand,moreimportantly,avoidsvariabilityintheCMlevelseenby-duetotheprecedingstage,thusmaintainingaconstant

0.25pFarerealizedusingtuningrange.Thecapacitors

multi-?ngerfringestructureshavingaparasiticcomponentofabout3%.TheCMlevelisgeneratedusingaresistivedivider.Thecornerfrequencyassociatedwiththiscapacitivecouplingisaround3MHz,resultinginnegligibledroopwithencodeddata.

B.EqualizerFilterII

InSectionII,thehigh-passpassivenetworkwasintroducedtoprovideapeakingpro?le.Theuseofthisnetworkintheequal-izer?ltercansavepowerconsumptionbyrelaxingthelinearityandgainpeakingrequirementsoftheactivestages.Fig.8showsthesecondequalizer?lterarchitecture[12],whichincorporatesbothpassivepeakingandreversescaling.Incontrasttothe?rstequalizer,thisdesignperformsboosttuningbyinterpolationbe-tweenapeakingpathandanall-passpath(setbycoef?cientsand),thusachievingawidertuningrangethanthatob-tainedbymeansofMOSvaractorsandvariableresistors.Also,aconstant(linear)degenerationresistanceinthedifferentialpairsyieldshigherlinearityandamoreaccurately-de?nedlow-fre-quencygain.

Theuseofinterpolationnonethelesspresentsadif?cultyfor

.Thedisparatede-intermediatelinelengths,i.e.,if

laysthroughthetwopathsresultinsubstantialISIaftertheircorrespondingoutputsaresummed.Realizedasadegenerateddifferentialpair,thephaseshiftblockintheall-passpathpar-tiallycorrectsthiserror.Thezeroofthisdifferentialpairispo-sitionedsuchthatthephaseresponseapproximatestheeffectiveresponseofthethreezerosinthepeakingpathforthefrequency

rangeof1–4GHz.Thepoleprovidesadditionaladjustmentoftheoverallphaseresponseintheall-passpath.7

Theuseofseriesinductivepeaking(with3-nHinductors)inthepassivebooststageallowswideinputtransistors(

m)inthe?rstdifferentialpairandhencereversescalingthroughthecascade.Thelow-frequencylossof7dBinthepassivenetworkdegradesthesensitivitytosomeextent.WithinductivepeakingandnegativeMillercapacitances,theband-widthofeachactivestagereaches18GHz.Thesummingstageincorporatesactivefeedback[10]toimprovethespeedwhileavoidinginductors.Sinceactivefeedbacktradeslow-frequencygainforbandwidth,ithasbeenappliedtoonlyonestage.

Thechoicebetweenthetwotypesofequalizersdescribedabovesomewhatdependsontheapplication.Theformerdoesnotincorporateapassivenetworkattheinput,providinggreatersensitivitybutconsumingahigherpower.Thelatterachievesahigherlinearityandwidertuningrange.

IV.ADAPTIVEEQUALIZER

Fig.9showsthe?rstadaptiveequalizerarchitecture[9],wheretheequalizer?lterisfollowedbyaslicer,andtwoloopscontroltheboostinthe?lterandtheswingintheslicer.The

,issensedatnodeAratherthanBbecauseequalizeddata,

theslicerincorporatessomepeakingtoimproveconvergenceoftheloops,therebyleadingtolargerjitteratBthanatAwhentheloopsreachsteadystate.Theneedfortheswingcontrolloopisjusti?edasfollows.

High-speedadaptiveequalizerssetthepeakinginthe?lterstagessoastocompensateforthehigh-frequencylossofthechannel.Tothisend,theequalizeroutputissharpenedbyaslicerandtheadaptationloopadjuststhepeakingaccordingtothe

indicatethata20Tlaymismatchproduceslessthan5psof

ISIjitterattheequalizeroutput.

7Simulations