Equalization and Clock and Data Recovery Techniques for 10-G

IEEEJOURNALOFSOLID-STATECIRCUITS,VOL.42,NO.9,SEPTEMBER20071999

EqualizationandClockandDataRecoveryTechniquesfor10-Gb/sCMOSSerial-LinkReceivers

SrikanthGondiandBehzadRazavi,Fellow,IEEE

Abstract—Twoequalizer?ltertopologiesandamergedequal-izer/CDRcircuitaredescribedthatoperateat10Gb/sin0.13-mCMOStechnology.Usingtechniquessuchasreversescaling,pas-sivepeakingnetworks,anddual-andtriple-loopadaptation,theprototypesadapttoFR4tracelengthsupto24inches.Theequal-izer/CDRcircuitretimesthedatawithabiterrorrateof1013whileconsuming133mWfroma1.6-Vsupply.

IndexTerms—Adaptiveequalization,analogequalization,broadbandreceivers,DFE,FFE,high-speedlinks,lossychannel,reversescaling.

withotherequalizationmethods[6]soastomitigatebotheffects.

SectionIIpresentsvariousgainpeakingmethodsthatareusedinSectionIIItodeveloptwoequalizer?ltertopologies.SectionIVdescribesanadaptiveequalizerarchitectureandSectionVthemergedequalizer/CDRcircuit.SectionVIsum-marizestheexperimentalresultsforthetwoprototypes.

II.GAINPEAKINGTECHNIQUES

A.GeneralConsiderations

CoppertracesdesignedastransmissionlinesonFR4sub-stratessufferfrombothskineffectanddielectricloss.Forex-ample,a30-intraceexhibitsalossofapproximately21dBat5GHzand34dBat10GHz(AppendixI).Theequalizer?ltermustthereforeprovideadequategainpeakingaround5GHzsoastoequalizethesignalspectrum.

Thedesignofgain-peakingcircuitsmustsatisfymanydif?cultrequirements:1)suf?cientboostathighfrequencies;2)matchingtheinverselosspro?leofthechannelwithreason-abletolerance;3)minimallow-frequencylosstominimizethenoiseaccumulationincascadedstagesandprovidesuf?cientswingsfortheCDR;4)well-behavedphaseresponsetoachievealowjitter;5)reasonablelinearitysothattheequalizertransferfunctionindeedactsastheinverseofthechannellosspro?le;

requirements;and6)smallinputcapacitancetosatisfythe

7)tunabilityoftheboosttoallowadaptation.

Inaddition,thechallengestypicallyencounteredinthedesignoflow-voltagebroadbandampli?ers–suchaslimitedbandwidthanddrivecapability–persisthereaswell.B.PeakingByComplexPolesorRealZeros

Theavailabilityofmonolithicinductorsmaysuggesttheuseofunderdampedcomplexpolestoprovidetherequiredboostathighfrequencies.Forexample,theshunt-peakingcircuitofFig.1(a)yieldsatransferfunctionoftheform

(1)

,,.Whileprovidingenoughboosttomatch

theinverseoftheFR4frequencyresponse,high-complexpolesintroducesubstantialphasedistortion.Asanexample,acascadeoftwosuchstagesisdesignedtoequalizea30-intrace[Fig.1(b)],yieldingtheequalizedeyeshowninFig.1(d).

Thisissuerestrictsrealizationstonon-feedbackstructurescontainingrealzerosandpolesorfeedbackstructureshavingwhere

I.INTRODUCTION

HEfrequency-dependentlossoftracesonFR4printedcir-cuitboards(PCBs)posesincreasinglymoredif?cultde-signchallengesasdataratesapproach10Gb/sandtracelengthsreachtensofinches.Preemphasisinthetransmittercanpartiallycompensateforthechannellossbutatthecostofdynamicrange.Forexample,the12dBpreemphasisin[1]requiresasupplyvoltageof2.5Vtoaccommodatethelargeampli?edcompo-nentswithoutsacri?cingthelow-frequencyswings.Thus,lowsupplyvoltagesandchannellossesashighas25dBdictatethatmostoftheequalizationbeperformedinthereceiver.Examplesincludeabipolarimplementationconsuming195mW[2]andaCMOSrealizationsufferingfromhighintersymbolinterference(ISI)andlackingautomaticadaptation[3].

Recentwork[1],[4],[5]hasincorporatednonlinear(e.g.,de-cision-feedback)equalizerssoastoaccommodatesharpnotchesinthechannelduetoimpedancediscontinuitiesandalsoavoidtheampli?cationofcrosstalkduetohigh-frequencypeaking.Thecomplexityandpowerdissipationofsuchrealizations(e.g.,210mWforthe6.25-Gb/s0.13-mCMOSreceiverin[5])arejusti?edforonlydemandingapplications.

Thispaperdescribesadaptiveequalizationandclockanddatarecovery(CDR)techniquessuitedto10-Gb/sbinaryreceivers.Theconceptsintroducedhereaddresstheproblemofhighlosses.Losscompensationisachievedbyusinglinearequalizationtechniquesthattendtoamplifycrosstalknoise.Ifcrosstalkandimpedancediscontinuitiesduetoconnectorsandviasalsobecomecritical,thesetechniquescanbecombined

ManuscriptreceivedJuly26,2006;revisedFebruary26,2007.ThisworkwassupportedbyKawasakiMicroelectronicsAmerica.FabricationsupportwasprovidedbyTaiwanSemiconductorManufacturingCompany.

S.GondiwaswiththeElectricalEngineeringDepartment,UniversityofCal-ifornia,LosAngeles,CA90095USA.HeisnowwithKawasakiMicroelec-tronics,SanJose,CA95131USA.

TheauthorsarewiththeElectricalEngineeringDepartment,UniversityofCalifornia,LosAngeles,CA90095USA(e-mail:razavi@icsl.ucla.edu).DigitalObjectIdenti?er10.1109/JSSC.2007.903076

T

0018-9200/$25.00?2007IEEE

2000IEEEJOURNALOFSOLID-STATECIRCUITS,VOL.42,NO.9,SEPTEMBER2007

Fig.1.Complexpolepeakingcircuit.(a)Implementation.(b)Magnituderesponse.(c)Phaseresponse.(d)transientresponse.

Fig.2.RC-degenerateddifferentialpair.(a)Circuitimplementation.(b)Fre-quencyresponse:actualresponse(solidline);bodeapproximation(dashedline).

low-complexpoles.Ofcourse,inductorscanstillactasshunt-peakingelementstobroadenthebandwidthofequalizerstages.Anef?cientmethodofboostingbymeansofrealzerosiscapacitivedegeneration.Fig.2(a)showsade-generateddifferentialpairthatyieldsazeroat

andpolesatand

,withalow-frequencygain

.Fig.2(b)depictsof

thefrequencyresponse.Improvingthelinearityofthestage,degenerationnonethelesscreatesatrade-offbetweenthe

.Interestingly,low-frequencygainandtheboostfactor,

onecanwrite

concludingthattheproductofthegain,theboostfactor,andthe

ofthetechnology.1bandwidthofthestageislimitedbythe

Itisimportanttoappreciatetheimpactofthelimited(about75GHzin0.13-mCMOStechnology)onequaliza-tion.Forasmall-signalgainof2,anundegenerateddifferen-tialpairwithanoverdrivevoltageof300mVandfanoutofunityyieldsabandwidthoflessthan12.5GHz.Thedegener-atedstructuretradesthisgain-bandwidthproductfortheboostfactor,thelow-frequencygain,andthelinearrange.