基于FPGA的恒虚警(CFAR)算法(5)

end

R9_add <= R10_add R11_add R12_add R13_add R14_add R15_add R16_add

R8_add ;

;

; ; ; ; ; ;

<= <= <= <= <= <= <=

R9_add R10_add R11_add R12_add R13_add R14_add R15_add

end

always @ (posedge I_clk or negedge I_rst_n) begin

if(~I_rst_n) begin end else begin end

if(R_add[18:3]>R16_add) begin end else begin end

R_average <=

R16_add;

R_average <=

R_add[18:3];

R_average <=

16'b0;

end

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always @ (posedge I_clk or negedge I_rst_n) begin if(~I_rst_n) begin R_signal

<=

16'b0

R1_signal <= 16'b0 ; R2_signal <= 16'b0 ; R3_signal <= 16'b0 ; R4_signal <= 16'b0 ; R5_signal <= 16'b0 ; R6_signal <= 16'b0 ; R7_signal <= 16'b0 ; R8_signal <= 16'b0 ; R9_signal <= 16'b0 ; R10_signal <= 16'b0 ; R11_signal <= 16'b0 ; R12_signal <= 16'b0 ; R13_signal <= 16'b0 ; R14_signal <= 16'b0 ; R15_signal <= 16'b0 ; R16_signal <=

16'b0

;

end else begin R_signal

<=

I_signal

R1_signal <= R_signal

R2_signal <= R1_signal ; R3_signal <= R2_signal ; R4_signal <= R3_signal ;

R5_signal <=

R4_signal ;

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;

; ;

end

R6_signal <= R7_signal <= R8_signal <= R9_signal <= R10_signal <= R11_signal <= R12_signal <= R13_signal <= R14_signal <= R15_signal <= R16_signal <=

R5_signal ; R6_signal ; R7_signal ; R8_signal ; R9_signal ; R10_signal ; R11_signal ; R12_signal ; R13_signal ; R14_signal ; R15_signal ;

end

always @ (posedge I_clk or negedge I_rst_n) begin

if(~I_rst_n) begin end else begin end

O_result

<=

R16_signal -

R_average;

O_result

<=

16'b0

;

end

Endmodule

先利用matlab生成噪声和信号数据，另存为txt文件。编写testbench，对程

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序进行仿真测试。Testbench程序如下：

module CFARTest;

// Outputs

wire [15:0] O_result;

parameter N=30; // Inputs reg I_rst_n; reg I_clk; reg [15:0] I_noise; reg [15:0] I_signal;

parameter S=10;

reg [15:0] NOISE_L[N-1:0];

reg [15:0] SIGNAL_L[S-1:0]; integer Index;

// Instantiate the Unit Under Test (UUT) CFAR uut ( );

always #5 I_clk = ~I_clk;

.I_rst_n(I_rst_n), .I_clk(I_clk), .I_noise(I_noise), .I_signal(I_signal), .O_result(O_result)

initial begin

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// Initialize Inputs I_rst_n = 0; I_clk = 0; I_noise = 0; I_signal = 0; Index = 0;

end

// Wait 100 ns for global reset to finish #100; I_rst_n

= 1

;

$readmemh(\$readmemh(\

//输入噪声

always@(posedge I_clk)

begin

if ((Index

begin

I_noise<=16'b0;

begin

I_noise<= NOISE_L[Index];

Index<=Index+1; end

end

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