基于FPGA的恒虚警(CFAR)算法(4)

I_rst_n , I_clk

I_noise , I_signal ,

O_result

);

input input

input[15:0] input[15:0] output[15:0] reg[15:0] reg[15:0] reg[15:0] reg[15:0] reg[15:0] reg[15:0] reg[15:0] reg[15:0] reg[15:0] reg[15:0] reg[15:0] reg[15:0] reg[15:0] reg[15:0] reg[15:0] reg[15:0] reg[19:0]

,

I_rst_n I_clk

I_noise I_signal O_result

O_result R_noise R1_noise R2_noise R3_noise R4_noise R5_noise R6_noise R7_noise R8_noise R9_noise

R10_noise R11_noise R12_noise R13_noise R14_noise R_add

; ;

; ; ;

; ; ; ; ; ; ; ; ; ;

;

; ; ; ; ;

;

9

reg[15:0] reg[15:0] reg[15:0] reg[15:0] reg[15:0] reg[15:0] reg[15:0] reg[15:0] reg[15:0] reg[15:0] reg[15:0] reg[15:0] reg[15:0] reg[15:0] reg[15:0] reg[15:0] reg[15:0] reg[15:0] reg[15:0] reg[15:0] reg[15:0] reg[15:0] reg[15:0] reg[15:0] reg[15:0] reg[15:0] reg[15:0] reg[15:0] reg[15:0] reg[15:0]

R1_add ; R2_add ; R3_add ; R4_add ; R5_add ; R6_add ; R7_add ; R8_add ; R9_add ; R10_add R11_add R12_add R13_add R14_add R15_add R16_add

R_average ; R_signal

R1_signal ; R2_signal ; R3_signal ; R4_signal ; R5_signal ; R6_signal ; R7_signal ; R8_signal ; R9_signal ; R10_signal ; R11_signal ; R12_signal ;

10

; ; ; ; ; ; ;

;

reg[15:0] reg[15:0] reg[15:0] reg[15:0]

R13_signal ; R14_signal ; R15_signal ; R16_signal ;

always @ (posedge I_clk or negedge I_rst_n) begin if(~I_rst_n) begin R_noise R1_noise R2_noise R3_noise R4_noise R5_noise R6_noise R7_noise R8_noise R9_noise

R10_noise R11_noise R12_noise R13_noise R14_noise end else begin R_noise R1_noise

R2_noise

<= 16'b0;

<= 16'b0; <= 16'b0; <= 16'b0; <= 16'b0; <= 16'b0; <= 16'b0; <= 16'b0; <= 16'b0;

<=

16'b0;

<= 16'b0; <= 16'b0; <= 16'b0; <= 16'b0; <=

16'b0;

<= I_noise ;

<= R_noise

<=

R1_noise

11

; ;

end

R3_noise R4_noise R5_noise R6_noise R7_noise R8_noise R9_noise

<= <= <= <= <= <= <=

R2_noise R3_noise R4_noise R5_noise R6_noise R7_noise R8_noise

;

; ; ; ; ; ; ;

R10_noise <= R11_noise <= R12_noise <= R13_noise <= R14_noise <=

R9_noise R10_noise; R11_noise; R12_noise; R13_noise;

end

always @ (posedge I_clk or negedge I_rst_n) begin

if(~I_rst_n) begin end else begin

R_add

<=

(I_noise + R_noise) + (R1_noise + R2_noise) +

R_add

<=

19'b0;

(R3_noise + R4_noise) + (R5_noise + R6_noise) + (R7_noise + R8_noise)+ (R9_noise + R10_noise)+ (R11_noise + R12_noise)+ (R13_noise + R14_noise);

end

end

always @ (posedge I_clk or negedge I_rst_n)

12

begin

if(~I_rst_n) begin end else begin

R1_add <= R2_add <= R3_add <= R4_add <= R5_add <= R6_add <= R7_add <= R8_add <=

R_add[19:4] ; R1_add R2_add R3_add R4_add R5_add R6_add R7_add

; ; ; ; ; ; ;

13

R1_add <= R2_add <= R3_add <= R4_add <= R5_add <= R6_add <= R7_add <= R8_add <= R9_add <= R10_add R11_add R12_add R13_add R14_add R15_add R16_add

16'b0; 16'b0; 16'b0; 16'b0; 16'b0; 16'b0; 16'b0; 16'b0; 16'b0;

16'b0; 16'b0; 16'b0; 16'b0; 16'b0; 16'b0; 16'b0;

<= <= <= <= <= <= <=