希洛·尤尔的基于VHDL的计程车计价器设计(14)

重庆邮电大学本科毕业设计（论文）

shown in colomn two of Table 2. the circuit, in this case, should supply a single pulse at the output M for every 100, 125 or 143 pulses generated at the input terminal E

according to the level of voltage at input terminale 3, K or L, respectively. Our circuit could be, as shown in Figure 5, three decade counters, connected as a three digit frequency divider whose dividing ratios 100, 125 and 143 are automatically selected by the voltage level at terminals J, K and L, respectively. A possible circuit diagram that may verify the above function is shown in Figure 6. It consists of three decade counters type 7490, one BCD-to decimal decoder type 7445, three 4-input AND, one 3-input ANDone 2-input AND two 3-input OR gates.

C. Time Scaling Circuit CT3

As shown in the block diagram, the time scalingcircuit will have four inputs J, K, L and F and one output N. The function of this circuit and accordingto colomn three of Table 2 (fare per 2 minuts of waiting time) is to supply a single pulse at the output N for every 120, 240 or 360 pulses supplied at the input terminal F from the I Hz clock according to level of voltage at inputs J, K and L, respectively.

Time scaling circuit would be similar to the distance scaling circuit but with different diving ratios. A Possible circuit diagram is shown in figure 7.

It consists, in this case, of three decade counter type 7490, two 3-input AND, one 5-input AND, one 2-input AND one 3-input OR gates.

D. Circuit CT4 Which Generates Clock Pulses for Display Circuit

The function of this circuit is to supply one, two or three pulses at the output terminal R for each pulse generated at any of the terminals N or M, according to the voltage level at the input terminals J, K or L, respectively. The output P will receive a pulse for each pulse generated at any of the input terminals N or M. This function can be performed by the circuit shown in Figure 8, it consists of one ripple counter type 7493, one half of a dual JK masterslave flip-flops circuit type 7476, three inverters, three 2-input AND, one 3-input AND, one 2-input OR and one 3-input OR gates. When a pulse is generated at either input terminals N or M, a high level voltage will be generated at the output Q of the flip-flop. This will g a t e t h e I Khz signal to be connected to the input A of the ripple counter as well as to the output terminal R. When one, two or three pulses are counted by the ripple counter, according to the level of voltage at the …… 此处隐藏：498字，全部文档内容请下载后查看。喜欢就下载吧 ……