基于FPGA的数字频率计的设计(8)

else unit_L<=1'b1; assign

unit_H=((count_a==4'd0)&&(count_b==4'd0)&&(count_c==4'd0)&&(count_d==4'd0));

always@(negedge gate or negedge rstn) begin

if(!rstn) gate_sel<=3'd0;

else if(unit_L&&(gate_sel!=3'd4)) gate_sel<=gate_sel+3'd1; else if(unit_H&&(gate_sel!=3'd0)) gate_sel<=gate_sel-3'd1; else gate_sel<=gate_sel; end

always@(gate_sel or div_10 or div_100 or div_1000 or div_10000 or div_100000) begin

case(gate_sel)

3'd0:gate=div_100000; 3'd1:gate=div_10000; 3'd2:gate=div_1000; 3'd3:gate=div_100; 3'd4:gate=div_10;

default:gate=div_100000; endcase end

wire d_n0_a,d_n0_b,d_n0_c,d_n0_d; wire a,b,c,d,e,f,g;

wire trans_ena_a,trans_ena_b,trans_ena_c,trans_ena_d; wire ena_a,ena_b,ena_c,ena_d; wire clk_lock;

assign clk_lock=~gate;

transform part_tran_a(.d_n0(d_n0_a),.din(count_a),.clk_lock(clk_lock),

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.ena(trans_ena_a),.a(a),.b(b),.c(c),.d(d),.e(e),.f(f),.g(g));

transform part_tran_b(.d_n0(d_n0_b),.din(count_b),.clk_lock(clk_lock), .ena(trans_ena_b),.a(a),.b(b),.c(c),.d(d),.e(e),.f(f),.g(g));

transform part_tran_c(.d_n0(d_n0_c),.din(count_c),.clk_lock(clk_lock), .ena(trans_ena_c),.a(a),.b(b),.c(c),.d(d),.e(e),.f(f),.g(g));

transform part_tran_d(.d_n0(d_n0_d),.din(count_d),.clk_lock(clk_lock), .ena(trans_ena_d),.a(a),.b(b),.c(c),.d(d),.e(e),.f(f),.g(g)); wire clk_ledc;

assign clk_ledc=div_1000;

led_sel part_led_sel(.rstn(rstn),.clk_ledc(clk_ledc),

.led_ena({ena_a,ena_b,ena_c,ena_d}),.led_count(led_sel)); assign trans_ena_a=ena_a&d_n0_a;

assign trans_ena_b=ena_b&(d_n0_b|d_n0_a); assign trans_ena_c=(d_n0_c|d_n0_b|d_n0_a)&ena_c; assign trans_ena_d=ena_d; endmodule

2. 分频模块源代码 module clk_gen( clk, rstn, div_10, div_100, div_1000, div_10000, div_100000, ); input clk,rstn; output div_10; output div_100; output div_1000;

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output div_10000; output div_100000; //div_10

reg[2:0] count1;

always@(posedge clk or negedge rstn) begin

if(!rstn) count1<=3'd0;

else if(count1==3'd4) count1<=3'd0;

else count1<=count1+3'd1; end

reg d1;

always@(posedge count1[2] or negedge rstn) begin

if(!rstn) d1<=1'd0; else d1<=~d1; end

assign div_10=d1; //div_100

reg[2:0] count2;

always@(posedge d1 or negedge rstn) begin

if(!rstn) count2<=3'd0;

else if(count2==3'd4) count2<=3'd0;

else count2<=count2+3'd1; end

reg d2;

always@(posedge count2[2] or negedge rstn) begin

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if(!rstn) d2<=1'd0; else d2<=~d2; end

assign div_100=d2; //div_1000

reg[2:0] count3;

always@(posedge d2 or negedge rstn) begin

if(!rstn) count3<=3'd0;

else if(count3==3'd4) count3<=3'd0;

else count3<=count3+3'd1; end

reg d3;

always@(posedge count3[2] or negedge rstn) begin

if(!rstn) d3<=1'd0; else d3<=~d3; end

assign div_1000=d3; //div_10000 reg[2:0] count4;

always@(posedge d3 or negedge rstn) begin

if(!rstn) count4<=3'd0;

else if(count4==3'd4) count4<=3'd0;

else count4<=count4+3'd1; end

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reg d4;

always@(posedge count4[2] or negedge rstn) begin

if(!rstn) d4<=1'd0; else d4<=~d4; end

assign div_10000=d4; //div_100000 reg[2:0] count5;

always@(posedge d4 or negedge rstn) begin

if(!rstn) count5<=3'd0;

else if(count5==3'd4) count5<=3'd0;

else count5<=count5+3'd1; end

reg d5;

always@(posedge count5[2] or negedge rstn) begin

if(!rstn) d5<=1'd0; else d5<=~d5; end

assign div_100000=d5; endmodule

3. 计数模块源代码 module count( clk, ena, rst,

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