基于FPGA的数字频率计的设计

基于FPGA的数字频率计的设计

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摘要

数字频率计是近代电子技术领域的重要测量工具之一，同时也是其它许多领域广泛应用的测量仪器。它在规定的基准时间内把测量的脉冲数记录下来，换算成频率并以数字形式显示出来。在许多测量方案以及测量结果中都会涉及到频率测量的相关问题，频率精确测量的重要性显而易见。

本设计在了解频率计的基本原理的基础上，基于直接测频法的测试手段，即在一定闸门时间内测量被测信号的脉冲个数；设计频率计的测量范围为1Hz-99.99MHz。将设计分为六个模块，即顶层模块，分频模块，计数模块，单位选择模块，数码管位选模块，转换模块。

采用硬件描述语言Verilog HDL编写了各个模块的代码，并且利用Quartus II软件平台进行了功能的仿真，从而完成输入被测频率，通过选择不同档位，精确输出测量值，达到了预期目标。

关键词 数字频率计；直接测频法；Verilog HDL；Quartus II

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Abstract

Digital frequency meter modern electronic technology is one of the important measurement tools and other areas widely used measuring instrument. It stipulated in the benchmark time to measure the number of pulses recording, the conversion into frequency and displayed in digital form. In many survey scheme and measurement results involve frequency measurements of related problems, the importance of accurate measurement of frequency is obvious.

This design in understanding the basic principle of the frequency meter, on the basis of direct frequency measurement method based on the means testing, that is, in a certain gate time measurement of the measured signal pulse number; Design the frequency meter measuring range of 1 Hz-99.99 MHz. Will design is divided into six parts, a top-level module, points frequency modules, count module, the unit choose module, digital tube a chosen module, conversion module

The hardware description language Verilog HDL write each module of the code, and make use of Quartus II software platform functions of the simulation. Then measured input frequency, by choosing different rank, precise output measured values, and reach the expected goal.

Keywords Digital frequency plan；Direct frequency measurement method ；Verilog HDL；Quartus II

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目录

摘要 ............................................................. I Abstract ........................................................ II

第1章 绪论 ...................................................... 1 1.1 课题背景和意义 .............................................. 1 1.2 国内外发展情况 .............................................. 1 第2章 频率计测量原理及Verilog HDL概述 .......................... 3 2.1 数字频率计测量原理 .......................................... 3 2.1.1 直接计数测频法 .......................................... 3 2.1.2 等精度测频法 ............................................ 5 2.1.3 全同步测频法 ............................................ 6 2.2 Verilog HDL概述 ............................................. 7 2.2.1 Verilog HDL介绍 .......................................... 7 2.2.2 Verilog HDL程序开发流程 .................................. 8 2.3 本章小结 .................................................... 8 第3章 数字频率计模块设计 ........................................ 9 3.1 数字频率计设计指标 .......................................... 9 3.2 数字频率计各个模块 ......................................... 10 3.2.1 顶层模块fre_counter ..................................... 10 3.2.2 分频模块clk_gen ........................................ 12 3.2.3 计数模块count .......................................... 14 3.2.4 单位控制模块count_4units ................................ 15 3.2.5 数码管位选模块led_sel ................................... 15 3.2.6 转换模块transform ....................................... 17 3.3 本章小结 ................................................... 18 第4章 数字频率计仿真 ........................................... 19 4.1 分频模块仿真波形 .......................................... 19 4.2 计数模块仿真波形 .......................................... 19

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4.3 单位控制模块仿真波形 ....................................... 20 4.4 数码管位选模块 ............................................. 20 4.5 转换模块 ................................................... 21 4.6 本章小结 ................................................... 21 第5章 芯片介绍和管脚分配 ....................................... 22 5.1 FPGA芯片介绍 ............................................. 22 5.2 代码管脚分配图 ............................................. 22 5.3 顶层原理图效果图 ........................................... 23 5.4 本章小结 .................................................. 23 结论 ............................................................ 24 致谢 ............................................................ 25 参考文献 ........................................................ 26 附录1 程序源代码 ................................................ 28

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