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数字信号处理英文翻译(4)

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导读: most modelling applications. Of course, the integrity of the hardware description language is the most complex chips from the integrity of the electronic systems described. history Verilog HDL langua

most modelling applications. Of course, the integrity of the hardware description language is the most complex chips from the integrity of the electronic systems described.

history

Verilog HDL language initially in 1983 by Gateway Design Automation companies for product development simulator hardware modelling language. Then it is only a dedicated language. Since their simulation, simulation devices widely used products, Verilog HDL as a user-friendly and practical language for many designers gradually accepted. In an effort to increase the popularity of the language activities, Verilog HDL language in 1990 was a public area. Open Verilog International (OVI) is to promote the development of Verilog international organizations. 1992, decided to promote OVI OVI standards as IEEE Verilog standards. The effort will ultimately succeed, a IEEE

1995 Verilog language standard, known as IEEE Std 1364-1995. Integrity standards in Verilog hardware description language reference manual contains a detailed description.

Main capacity:

Listed below are the main Verilog hardware description language ability

*Basic logic gate, and, for example, or have embedded in the language and nand

* Users of the original definition of the term (UDP), the flexibility. Users can be defined in the original language combinations logic original language, the original language of logic could also be time series

* Switches class infrastructure models, such as the nmos and pmos also be embedded in the language

* Hin-language structure designated for the cost of printing the design and trails Shi Shi and design time series checks.

* Available three different ways to design or mixed mode modelling. These methods include : acts described ways - use process of structural modelling; Data flow approach - use of a modelling approach Fuzhi expression; Structured way - using examples of words to describe modular doors and modelling.

* Verilog HDL has two types of data : data types and sequence data line network types. Line network types that the physical links between components and sequence types that abstract data storage components.

* To describe the level design, the structure can be used to describe any level module example

数字信号处理第一章 滤波器的基本概念,数字滤波器的仿真与实现The simulation and the realization of the digital filter英文翻译,中文英文对照

* Design size can be arbitrary; Language is design size (size) impose any restrictions

* Verilog HDL is no longer the exclusive language of certain companies but IEEE standards. * And the machine can read Verilog language, it may as EDA tools and languages of the world between the designers

* Verilog HDL language to describe capacity through the use of programming language interface (PLI) mechanism further expansion. PLI is to allow external functions of the visit Verilog module information, allowing designers and simulator world Licheng assembly

* Design to be described at a number of levels, from the switch level, doors level, register transfer level (RTL) to the algorithm level, including the level of process and content

* To use embedded switching level of the original language in class switch design integrity modelling

* Same language can be used to generate simulated incentive and certification by the designated testing conditions, such as the value of imports of the designated

*Verilog HDL simulation to monitor the implementation of certification, the certification process of implementing the simulation can be designed to monitor and demonstrate value. These values can be used to compare with the expectations that are not matched in the case of print news reports.

* Acts described in the class, not only in the RTL level Verilog HDL design description, and to describe their level architecture design algorithm level behavioural description

* Examples can use doors and modular structure of language in a class structure described

* Verilog HDL mixed mode modelling capabilities in the design of a different design in each module can level modelling

* Verilog HDL has built-in logic function, such as

*Structure of high-level programming languages, such as conditions of expression, and the cycle of expression language, language can be used

* To it and can display regular modelling

* Provide a powerful document literacy

* Language in the specific circumstances of non-certainty that in the simulator, different models can produce different results; For example, describing events in the standard sequence of events is not defined.

5、In troduction of DSP

数字信号处理第一章 滤波器的基本概念,数字滤波器的仿真与实现The simulation and the realization of the digital filter英文翻译,中文英文对照

Today, DSP is w idely used in the modern techno logy and it has been the key part of many p roducts and p layed more and mo re impo rtant ro le in our daily life.Recent ly, Northw estern Po lytechnica lUniversity Aviation Microelect ronic Center has comp leted the design of digital signal signal p rocesso r co re NDSP25, w h ich is aim ing at TM S320C25 digital signal p rocesso r of Texas Inst rument TM S320 series. By using top 2dow n design flow , NDSP25 is compat ible w ith inst ruct ion and interface t im ing of TM S320C25.

Digital signal processors (DSP) is a fit for real-time digital signal processing for high-speed dedicated processors, the main variety used for real-time digital signal processing to achieve rapid algorithms. In today's digital age background, the DSP has become the communications, computer, and consumer electronics products, and other fields based device.

Digital signal processors and digital signal processing is inseparably, we usually say "DSP" can also mean the digital signal processing (Digital Signal Processing), is that in this digital …… 此处隐藏:6127字,全部文档内容请下载后查看。喜欢就下载吧 ……

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