数字信号处理英文翻译(3)

means stability operations in the chip design can achieve the highest frequency, the frequency of the time series design situation, and design to meet the clock cycle -- PADto pad, Clock Setup Time, Clock Hold Beijing, Clock-to-Output Delay, and other characteristics of many time series closely related. Area (area) and speed (speed) runs through the two targets FPGA design always is the ultimate design quality evaluation criteria. On the size and speed of the two basic concepts : balance of size and speed and size and speed of swap.

One pair of size and speed is the unity of opposites contradictions body. Requirements for the design of a design while the smallest, highest frequency of operation is unrealistic. More scientific goal should be to meet the design requirements of the design time series (includes requirements for the design frequency) premise, the smallest chip area occupied. Or in the specified area, the design time series cushion greater frequency run higher. This fully embodies the goals of both size and speed balanced thinking. On the size and speed requirements should not be simply interpreted as raising the level and design engineers perfect sexual pursuit, and should recognize that they are products and the quality and cost of direct relevance. If time series cushion larger design, running relatively high frequency, that the design Jianzhuangxing stronger, more quality assurance system as a whole; On the other hand, the smaller size of consumption design is meant to achieve in chip unit more functional modules, the chip needs fewer, the entire system has been significantly reduced cost. As a contradiction of the two components, the size and speed is not the same status. In contrast, meet the timetables and work is more important for some frequency when both conflicts, the use of priority guidelines.

Area and the exchange rate is an important FPGA design ideas. Theoretically, if a design time series cushion larger, can run much higher than the frequency design requirements, then we can through the use of functional modules to reduce the consumption of the entire chip design area, which is used for space savings advantages of speed; Conversely, if the design of a time series demanding, less than ordinary methods of design frequency then generally flow through the string and data conversion, parallel reproduction of operational module, designed to take on the whole "string and conversion" and operate in the export module to chip in the data "and string conversion" from the macro point of view the whole chip meets the requirements of processing speed, which is equivalent to the area of reproduction - rate increase.

For example. Assuming that the digital signal processing system is 350Mb/s input data flow rate, and in FPGA design, data processing modules for maximum processing speed of

数字信号处理第一章 滤波器的基本概念,数字滤波器的仿真与实现The simulation and the realization of the digital filter英文翻译,中文英文对照

150Mb/s, because the data throughput processing module failed to meet requirements, it is impossible to achieve directly in the FPGA. Such circumstances, they should use "area-velocity" thinking, at least three processing modules from the first data sets will be imported and converted, and then use these three modules parallel processing of data distribution, then the results "and string conversion," we have complete data rate requirements. We look at both ends of the processing modules, data rate is 350Mb/s, and in view of the internal FPGA, each sub-module handles the data rate is 150Mb/s, in fact, all the data throughput is dependent on three security modules parallel processing subsidiary completed, that is used by more chip area achieve high-speed processing through "the area of reproduction for processing speed enhancement" and achieved design.

FPGA is the English abbreviation Field of Programmable Gate Array for the site programmable gate array, which is in Pal, Gal, Epld, programmable device basis to further develop the product. It is as ASIC (ASIC) in the field of a semi-customized circuit and the emergence of both a customized solution to the shortage circuit, but overcome the original programmable devices doors circuit few limited shortcomings.

FPGA logic module array adopted home (Logic Cell Array), a new concept of internal logic modules may include CLB (Configurable Logic Block), export import module IOB (Input Output Block) and internal links (Interconnect) 3. FPGA basic features are :

(1) Using FPGA ASIC design ASIC using FPGA circuits, the chip can be used,while users do not need to vote films production.

(2) FPGA do other customized or semi-customized ASIC circuits throughout the Chinese specimen films.

3) FPGA internal capability and rich I/O Yinjue.

4) FPGA is the ASIC design cycle, the shortest circuit, the lowest development costs, risks among the smallest device

5) FPGA using high-speed Chmos crafts, low consumption, with CMOS, TTL low-power compatible

It can be said that the FPGA chip is for small-scale systems to improve system integration, reliability one of the best

Currently FPGA many varieties, the Revenue software series, TI companies TPC series, the fiex ALTERA company series

数字信号处理第一章 滤波器的基本概念,数字滤波器的仿真与实现The simulation and the realization of the digital filter英文翻译,中文英文对照

FPGA is stored in films from the internal RAM procedures for the establishment of the state of its work, therefore, need to programmed the internal Ram. Depending on the different configuration, users can use a different programming methods

Plus electricity, FPGA, EPROM chips will be read into the film, programming RAM中 data, configuration is completed, FPGA into working order. Diaodian, FPGA resume into white films, the internal logic of relations …… 此处隐藏：6008字，全部文档内容请下载后查看。喜欢就下载吧 ……