Parallelization of AESA (Active Electronically Scanned Array(2)

Programming Tools

DOL (Distributed Operation layer) A framework from ETHZ for programming of parallel applications and specify how they are mapped on a multicore architecture

System Application Architecture a mapping

Process Network with XML schema DOLExample of process network

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有源相控阵雷达的并行信号处理(利用DOL-BIP工具)。(可公开检索到并能够免费下载的一个PPT文件)所谓的并行就是先进行数字波束形成DBF,产生多个并行波束通道,每个通道利用多普勒滤波器组进行并行信号处理,之后脉冲压缩,再经过恒虚警处理进行目标检测。跟常规处理方法似乎也没什么大的差别,处理顺序略有调整,原理上没啥新鲜,但资料公开时间还算挺近的。

Source: Verimag/ UJF<port type="input" name="1"/><port type="output" name="2"/><source type="c" location="square.c"/></process>… generator C1 square C2 consumer<memory name="sc_mem1" type="CACHE"><!-- sw_channels --><configuration name="cycles" value="1"/><sw_channel type="fifo" size="10" name="C1"></memory><port type="input" name="0"/> Architecture model: Computation resources interconnected according to communication paths (XML<port type="output" name="1"/> description)<hw_channel name="lbus1" type="BUS"></sw_channel> Comm path sepcifies<configuration name="frequency" communication between CPU’s using a common memory… value="200000000"/><connection name="g-c"><configuration name="bytespercycle"<origin name="generator"> value="1"/><port Tile1 Tile2 name="1"/></hw_channel> ARM1 ARM2</origin>…<target name="C1"><!-- distributed external memory --><port name="0"/><memory name="sh_mem" type="RAM"> Local Bus (LB1) Local Bus (LB2)</target><configuration name="cycles" value="1"/>…</connection><!--configuration name="cycles" value="6"/<!-- process bindings --> Shared Local Local… -><binding name="binding_generator" Mem Mem Mem</memory> xsi:type="computation"> (SM) (LM1) (LM2)<process name="generator"/><!-- bus --><processor name="ARM1"/><hw_channel name="ahb" type="BUS"> Shard Bus</binding><configuration name="frequency"… value="100000000"/><!-- channel bindings --><configuration name="bytespercycle"<binding name="binding_fifoC1" value="4"/> xsi:type="communication"> Mapping: hw-memories (XML description)</hw_channel> Allocation of sw-process to hw-processor, sw-channels to<sw_channel name=”C1"/>…<writepath name="pm1ahbsh_mem"/><readpath name="sh_memahbpm2"/></binding>…<processor name="ARM1" type="RISC"><configuration name="memory" value="pm1"/

></processor>… Application model: Process network of sw-processes, sw-channels and connections (XML), process<process name="square"> behavior<!-- arm core 1 --> (C file per process)

source: Verimag

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有源相控阵雷达的并行信号处理(利用DOL-BIP工具)。(可公开检索到并能够免费下载的一个PPT文件)所谓的并行就是先进行数字波束形成DBF,产生多个并行波束通道,每个通道利用多普勒滤波器组进行并行信号处理,之后脉冲压缩,再经过恒虚警处理进行目标检测。跟常规处理方法似乎也没什么大的差别,处理顺序略有调整,原理上没啥新鲜,但资料公开时间还算挺近的。

Generation of Application SW ModelApplication SW Mapping Architecture

DOLHW Component Library HdS Component Library

dol2bip Source: Verimag/ UJF Application SW Model Native BIP Simulation Transformation System Model Instrumentation: API, Observer injection Instrumented System Model Native BIP Simulation Performance ResultsPage 14 (10)

Translation HW Architecture Model

Code Generation

Multithreaded application code

HdS Code

有源相控阵雷达的并行信号处理(利用DOL-BIP工具)。(可公开检索到并能够免费下载的一个PPT文件)所谓的并行就是先进行数字波束形成DBF,产生多个并行波束通道,每个通道利用多普勒滤波器组进行并行信号处理,之后脉冲压缩,再经过恒虚警处理进行目标检测。跟常规处理方法似乎也没什么大的差别,处理顺序略有调整,原理上没啥新鲜,但资料公开时间还算挺近的。

Illustrated Example

Parallelization of AESA using DOL/BIP (DBF - DFB)

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有源相控阵雷达的并行信号处理(利用DOL-BIP工具)。(可公开检索到并能够免费下载的一个PPT文件)所谓的并行就是先进行数字波束形成DBF,产生多个并行波束通道,每个通道利用多普勒滤波器组进行并行信号处理,之后脉冲压缩,再经过恒虚警处理进行目标检测。跟常规处理方法似乎也没什么大的差别,处理顺序略有调整,原理上没啥新鲜,但资料公开时间还算挺近的。

Digital Beam FormingElement 1 Beam 1

Element 2

Wy,xWeight Matrix (pre-calculated)

Beam 2

Indata

Output

Element x x is number of antenna elements

Beam y y is number of beams

Break the input data to x number of antenna elements Weight matrix consists of y row and x columns When sample i of all antenna elements arrive, they will be multiplied with corresponding weight vector to produce corresponding sample of all the beams The process is repeated until all the all samples (Npulses x Nranges) are produced

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有源相控阵雷达的并行信号处理(利用DOL-BIP工具)。(可公开检索到并能够免费下载的一个PPT文件)所谓的并行就是先进行数字波束形成DBF,产生多个并行波束通道,每个通道利用多普勒滤波器组进行并行信号处理,之后脉冲压缩,再经过恒虚警处理进行目标检测。跟常规处理方法似乎也没什么大的差别,处理顺序略有调整,原理上没啥新鲜,但资料公开时间 …… 此处隐藏：3542字，全部文档内容请下载后查看。喜欢就下载吧 ……