RECONFIGURATION FOR POWER SAVING IN REAL-TIME MOTION ESTIMAT

Motion estimation presents a class of algorithms well-suited to reconfigurable hardware due to their variable computational load, highly structured array architectures, robust reduced complexity algorithms, and a motivation for low power implementations in

RECONFIGURATION FOR POWER SAVING IN REAL-TIME MOTION ESTIMATIONS.R. Park and W. Burleson

Department of Electrical and Computer Engineering University of Massachusetts at Amherst, MA 01003 fsrpark, burlesong@ecs.umass.eduMotion estimation presents a class of algorithms well-suited to recon gurable hardware due to their variable computational load, highly structured array architectures, robust reduced complexity algorithms, and a motivation for low power implementations in portable video products. Motion estimation is the most computationally demanding part of video compression algorithms and hence usually requires hardware support for real-time implementation. However dedicated hardware usually requires that the algorithm and most of its parameters be hardwired. Recon gurable hardware based on FPGAs allows the parallelism of hardware implementations with the exibility of software. The statistics of motion vectors can be monitored on a frame by frame basis to choose appropriate algorithm and hardware con gurations. Unlike some proposed applications of dynamic recon guration, this rate can easily be supported by existing FPGA technology. Another novel aspect of this work is that we use power savings as a motivation for the recon guration. Although FPGAs are not a very power e cient technology, careful design of array architectures can allow power to be saved by avoiding unnecessary computation by adjusting the search area according to the changing characteristics of an input video signal. Another more general result is that further power saving can be achieved by utilizing free FPGA resources as local memory to avoid power-hungry o -chip communication. Practical implementation issues using Xilinx 6200 series FPGAs are also discussed.

ABSTRACT

not have exibility at all or have only a small amount of exibility. Most signi cantly, the search area size can not be varied at run-time. If the search area can be adjusted dynamically according to the changing characteristics of an input video signal, the search area size can be tailored to avoid unnecessary computation, and hence power saving without severe loss of picture quality. In this paper, we propose a recon gurable approach to motion estimation. Rather than proposing new architectures or new matching criteria, we focus on how recon gurability can be exploited in motion estimation with wellknown architecture and matching criteria. The power saving due to recon guration is analyzed by using a simple model.

2. MOTION ESTIMATIONFor estimating motion by means of a block matching algorithm, the image is divided into blocks of n n pixels. Usually n is 16. The blocks resulting from the segmentation of the current and previous frames are called the current and previous block, respectively. For each current block, the best matching previous block is found within a search area surrounding the previous block. The previous blocks in a search area are called candidate blocks. Suppose the search area extends

on both sides over p pixels in the horizontal and vertical directions, then the search area is (2p+ n)2, and the total number of the candidate blocks in search area is (2p+ 1)2 . If the picture size is M by N pixels, then the number of blocks in one frame is M N=n2 . We assume that M and N are integer multiples of n throughout this paper. To compute the motion vector, the Mean Absolute Difference (MAD) criterion is widely used.D k; l

1. INTRODUCTIONVisual communication is a rapidly growing area for telecommunications, computers and multimedia. There are now several video compression standards such as H.261, MPEG1 and MPEG-2, which are all based on block based motion compensation and Discrete Cosine Transform(DCT) to reduce the temporal and spatial redundancy, respectively 1]. To reduce the enormous date rate of a video signal, DCT is used in intraframe coding and motion estimation/compensation is used in interframe coding. Motion estimation is the most computationally demanding part of video coding. It exploits temporal correlation between two consecutive frames and provides a large (typically a factor of ve) coding e ciency 2]. Most motion estimation algorithms implemented in VLSI up to now do

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Vmin= (k; l )Dmin (2) where x(i; j ) is the luminance value of a pixel in the current block and y(i+ k; j+ l) is the luminance value of a pixel in the candidate block. Vmin is called the motion vector. The displacement calculated is limited to a search area range such that?p k; l p. Fig.1 shows a block and a block matching algorithm. Basically block matching algorithms can be divided into two categories: full search block matching algorithm(FS BMA) and`intelligent' or`directed' search

Motion estimation presents a class of algorithms well-suited to reconfigurable hardware due to their variable computational load, highly structured array architectures, robust reduced complexity algorithms, and a motivation for low power implementations in

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Motion estimation presents a class of algorithms well-suited to reconfigurable hardware due to their variable computational load, highly structured array architectures, robust reduced complexity algorithms, and a motivation for low power implementations in

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BlockM Block(a)(b)(c)normalized power vs. search area(p)4.03.5

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