SST25VF512-20-4C-SAE;SST25VF512-20-4C-SAE-T;中文规格书,Datas

512KbitSPISerialFlash

A Microchip Technology Company

SST25VF512

DataSheet

SST serial flash family features a four-wire, SPI-compatible interface that allowsfor a low pin-count package occupying less board space and ultimately loweringtotal system costs. SST25VF512 SPI serial flash memory is manufactured withSST's proprietary, high-performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and man-ufacturability compared with alternate approaches.

Features

Single2.7-3.6VReadandWriteOperations SerialInterfaceArchitecture

–SPICompatible:Mode0andMode3

End-of-WriteDetection

–SoftwareStatus

HoldPin(HOLD#)

–Suspendsaserialsequencetothememorywithoutdeselectingthedevice

20MHzMaxClockFrequency SuperiorReliability

–Endurance:100,000Cycles(typical)–Greaterthan100yearsDataRetention

WriteProtection(WP#)

–Enables/DisablestheLock-Downfunctionofthestatusregister

LowPowerConsumption:

–ActiveReadCurrent:7mA(typical)–StandbyCurrent:8µA(typical)

SoftwareWriteProtection

–WriteprotectionthroughBlock-Protectionbitsinstatusregister

FlexibleEraseCapability

–Uniform4KBytesectors

–Uniform32KByteoverlayblocks

PackagesAvailable

–8-leadSOIC(4.9mmx6mm)–8-contactWSON

FastEraseandByte-Program:

–Chip-EraseTime:70ms(typical)

–Sector-orBlock-EraseTime:18ms(typical)–Byte-ProgramTime:14µs(typical)

Allnon-Pb(lead-free)devicesareRoHScompliant

AutoAddressIncrement(AAI)Programming

–DecreasetotalchipprogrammingtimeoverByte-Pro-gramoperations

DataSheet

ProductDescription

SST’sserialflashfamilyfeaturesafour-wire,SPI-compatibleinterfacethatallowsforalowpin-countpackageoccupyinglessboardspaceandultimatelyloweringtotalsystemcosts.SST25VF512SPIserialflashmemoryismanufacturedwithSST’sproprietary,high-performanceCMOSSuperFlashtechnology.Thesplit-gatecelldesignandthick-oxidetunnelinginjectorattainbetterreliabilityandman-ufacturabilitycomparedwithalternateapproaches.

TheSST25VF512devicesignificantlyimprovesperformance,whileloweringpowerconsumption.Thetotalenergyconsumedisafunctionoftheappliedvoltage,current,andtimeofapplication.Sinceforanygivenvoltagerange,theSuperFlashtechnologyuseslesscurrenttoprogramandhasashortererasetime,thetotalenergyconsumedduringanyEraseorProgramoperationislessthanalternativeflashmemorytechnologies.TheSST25VF512deviceoperateswithasingle2.7-3.6Vpowersupply.TheSST25VF512deviceisofferedinboth8-leadSOICand8-contactWSONpackages.SeeFigure1forthepinassignments.

DataSheet

BlockDiagram

DataSheet

PinDescription

CE#SOWP#VSS

12

87

VDDHOLD#SCKSI

CE#SOWP#VSS

VDDHOLD#SCKSI

TopView

34

65

119208-soicP1.4

TopView

119208-wsonP1a.6

8-leadSOIC

8-contactWSON

Figure1:PinAssignmentsTable1:PinDescription

DataSheet

MemoryOrganization

TheSST25VF512SuperFlashmemoryarrayisorganizedin4KBytesectorswith32KByteoverlayblocks.

DeviceOperation

TheSST25VF512isaccessedthroughtheSPI(SerialPeripheralInterface)buscompatibleprotocol.TheSPIbusconsistoffourcontrollines;ChipEnable(CE#)isusedtoselectthedevice,anddataisaccessedthroughtheSerialDataInput(SI),SerialDataOutput(SO),andSerialClock(SCK).TheSST25VF512supportsbothMode0(0,0)andMode3(1,1)ofSPIbusoperations.Thedifferencebetweenthetwomodes,asshowninFigure2,isthestateoftheSCKsignalwhenthebusmasterisinStand-bymodeandnodataisbeingtransferred.TheSCKsignalislowforMode0andSCKsignalishighforMode3.Forbothmodes,theSerialDataIn(SI)issampledattherisingedgeoftheSCKclocksignalandtheSerialDataOutput(SO)isdrivenafterthefallingedgeoftheSCKclocksignal.

DataSheet

HoldOperation

HOLD#pinisusedtopauseaserialsequenceunderwaywiththeSPIflashmemorywithoutresettingtheclockingsequence.ToactivatetheHOLD#mode,CE#mustbeinactivelowstate.TheHOLD#modebeginswhentheSCKactivelowstatecoincideswiththefallingedgeoftheHOLD#signal.TheHOLDmodeendswhentheHOLD#signal’srisingedgecoincideswiththeSCKactivelowstate.IfthefallingedgeoftheHOLD#signaldoesnotcoincidewiththeSCKactivelowstate,thenthedeviceentersHoldmodewhentheSCKnextreachestheactivelowstate.Similarly,iftherisingedgeoftheHOLD#signaldoesnotcoincidewiththeSCKactivelowstate,thenthedeviceexitsinHoldmodewhentheSCKnextreachestheactivelowstate.SeeFigure3forHoldConditionwaveform.

OncethedeviceentersHoldmode,SOwillbeinhigh-impedancestatewhileSIandSCKcanbeVILorVIH.IfCE#isdrivenactivehighduringaHoldcondition,itresetstheinternallogicofthedevice.AslongasHOLD#signalislow,thememoryremainsintheHoldcondition.Toresumecommunicationwiththedevice,HOLD#mustbedrivenactivehigh,andCE#mustbedrivenactivelow.SeeFigure17forHoldtiming.

Figure3:HoldConditionWaveform

WriteProtection

TheSST25VF512providessoftwareWriteprotection.TheWriteProtectpin(WP#)enablesordisablesthelock-downfunctionofthestatusregister.TheBlock-Protectionbits(BP1,BP0,andBPL)inthesta-tusregisterprovideWriteprotectiontothememoryarrayandthestatusregister.SeeTable3forBlock-Protectiondescription.

WriteProtectPin(WP#)

TheWriteProtect(WP#)pinenablesthelock-downfunctionoftheBPLbit(bit7)inthestatusregister.WhenWP#isdrivenlow,theexecutionoftheWrite-Status-Register(WRSR)instructionisdeterminedbythevalueoftheBPLbit(seeTable2).WhenWP#ishigh,thelock-downfunctionoftheBPLbitisdisabled.

Table2:ConditionstoexecuteWrite-Status-Register(WRSR)Instruction

T2.0

25076

DataSheet

StatusRegister

ThesoftwarestatusregisterprovidesstatusonwhethertheflashmemoryarrayisavailableforanyReadorWriteoperation,whetherthedeviceisWriteenabled,andthestateofthememoryWritepro-tection.DuringaninternalEraseorProgramoperation,thestatusregistermaybereadonlytodeter-minethecompletionofanoperationinprogress.Table4describesthefunctionofeachbitintheso …… 此处隐藏：8414字，全部文档内容请下载后查看。喜欢就下载吧 ……