hardware+design+with+SOPC+builder

来源：网络收集时间：2026-09-01

导读： hardware+design+with+SOPC+builder Section 2 Hardware Design with SOPC Builder Copyright 2005 Altera Corporation hardware+design+with+SOPC+builder Section 2 - TopicsCreate a Quartus Project Create a NiosII system in SOPC Builder Create a Ni

hardware+design+with+SOPC+builder

Section 2

Hardware Design with SOPC Builder

hardware+design+with+SOPC+builder

Section 2 - TopicsCreate a Quartus Project Create a NiosII system in SOPC Builder Create a NiosII software project Run as Instruction Set Simulator (ISS) RTL Simulation

hardware+design+with+SOPC+builder

Reference Designs For Dev KitsSeveral reference designs are available See altera\kits\nios2\examples\verilog or altera\kits\nios2\examples\vhdl

hardware+design+with+SOPC+builder

Standard and Custom Peripherals

hardware+design+with+SOPC+builder

SOPC Builder Development Tool

hardware+design+with+SOPC+builder

Avalon Master-Slave ConnectionsView=> Show Master Connections Observe and configure Avalon connections

hardware+design+with+SOPC+builder

Configure the Nios II CPUHardware designer selects Nios II version economy, standard, or fast

hardware+design+with+SOPC+builder

Choose JTAG Debug CoreSelect appropriate JTAG Debug level when configuring Nios II processor core

hardware+design+with+SOPC+builder

Select Cache and TCM SettingsAdjust Size of Instruction and Data Cache Memory Can now completely disable data cache on fast core And also disable instruction cache as long as TCM used

Enable Instruction/ Data Tightly Coupled Memory masters Control Data Cache Width Up to 32 byte cache line width now possible for better burst support

hardware+design+with+SOPC+builder

SOPC Builder– Board SettingsAllows you to connect SOPC Builder components directly to board components using Pin Mapper utility

hardware+design+with+SOPC+builder

Using Pin MapperPin Editor contains three columns SOPC Name, PCB Component, Component PinSOPC Builder component name and port names PCB Component Name and Ref-Des PCB pin names

hardware+design+with+SOPC+builder

Assignments get made in QSFDuring generation, all corresponding Quartus II pin assignments get made in the .QSF file.

hardware+design+with+SOPC+builder

SOPC Builder– More“cpu” SettingsSet Reset, Exception, and Break Location addresses Note: Reset must be in non-volatile memory

hardware+design+with+SOPC+builder

Nios II Exception Address All exceptions processed by code at“exception location” Provided by HAL system library

Supported Exception TypesSoftware Exceptions Software Traps (currently, not implemented) Unimplemented instructions Maintains compatibility between Nios II cores

Hardware Interrupts 32 Level-sensitive interrupts are supported.

hardware+design+with+SOPC+builder

SOPC Builder– System GenerationGenerate HDL Code/block symbol file and/or ModelSim Simulation Project Note: Can also launch Nios II IDE from here

hardware+design+with+SOPC+builder

Peripherals for Nios II

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