AD9520-2BCPZ;AD9520-2BCPZ-REEL7;AD9520-2PCBZ;中文规格书,Data

12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.2 GHz VCO

AD9520-2

FUNCTIONAL BLOCK DIAGRAM

FEATURES

Low phase noise, phase-locked loop (PLL)

On-chip VCO tunes from 2.02 GHz to 2.335 GHz Supports external 3.3 V/5 V VCO/VCXO to 2.4 GHz 1 differential or 2 single-ended reference inputs

Accepts CMOS, LVDS, or LVPECL references to 250 MHz Accepts 16.67 MHz to 33.3 MHz crystal for reference input Optional reference clock doubler Reference monitoring capability

Auto and manual reference switchover/holdover modes, with selectable revertive/nonrevertive switching Glitch-free switchover between references Automatic recovery from holdover

Digital or analog lock detect, selectable Optional zero delay operation

Twelve 1.6 GHz LVPECL outputs pided into 4 groups Each group of 3 has a 1-to-32 pider with phase delay Additive output jitter as low as 225 fs rms

Channel-to-channel skew grouped outputs <16 ps

Each LVPECL output can be configured as 2 CMOS outputs (for fOUT ≤ 250 MHz)

Automatic synchronization of all outputs on power-up Manual synchronization of outputs as needed SPI- and I²C-compatible serial control port 64-lead LFCSP

Nonvolatile EEPROM stores configuration settings

07215-001

Figure 1.

APPLICATIONS

Low jitter, low phase noise clock distribution

Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols Forward error correction (G.710)

Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers ATE and high performance instrumentation Broadband infrastructures

The AD9520 serial interface supports both SPI and I2C® ports. An in-package EEPROM can be programmed through the serial interface and store user-defined register settings for power-up and chip reset.

The AD9520 features 12 LVPECL outputs in four groups. Any of the 1.6 GHz LVPECL outputs can be reconfigured as two 250 MHz CMOS outputs.

Each group of outputs has a pider that allows both the pide ratio (from 1 to 32) and the phase (coarse delay) to be set. The AD9520 is available in a 64-lead LFCSP and can be operated from a single 3.3 V supply. The external VCO can have an operating voltage up to 5.5 V. A separate output driver power supply can be from 2.375 V to 3.465 V.

The AD9520 is specified for operation over the standard industrial range of 40°C to +85°C.

GENERAL DESCRIPTION

The AD9520-2 provides a multioutput clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 2.02 GHz to 2.335 GHz. An external 3.3 V/5 V VCO/VCXO of up to 2.4 GHz can also be used.

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The AD9520 is used throughout this data sheet to refer to all the members of the AD9520 family. However, when AD9520-2 is used, it is referring to that specific member of the AD9520 family.

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Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD9520-2

Theory of Operation ...................................................................... 28 Operational Configurations ...................................................... 28 Mode 0: Internal VCO and Clock Distribution ................. 28 Mode 1: Clock Distribution or External VCO

< 1600 MHz ............................................................................ 30 Mode 2: High Frequency Clock Distribution—

CLK or External VCO > 1600 MHz .................................... 32 Phase-Locked Loop (PLL) .................................................... 34 Configuration of the PLL ...................................................... 34 Phase Frequency Detector (PFD) ........................................ 34 Charge Pump (CP) ................................................................. 35 On-Chip VCO ........................................................................ 35 PLL External Loop Filter ....................................................... 35 PLL Reference Inputs ............................................................. 35 Reference Switchover ............................................................. 36 Reference Divider R ............................................................... 36 VCO/VCXO Feedback Divider N: P, A, B, R ..................... 36 Digital Lock Detect (DLD) ................................................... 38 Analog Lock Detect (ALD) ................................................... 38 Current Source Digital Lock Detect (CSDLD) .................. 38 External VCXO/VCO Clock Input (CLK/CLK) ................ 39 Holdover .................................................................................. 39 External/Manual Holdover Mode ........................................ 39 Automatic/Internal Holdover Mode .................................... 39 Frequency Status Monitors ................................................... 41 VCO Calibration .................................................................... 42 Zero Delay Operation ................................................................ 43 Internal Zero Delay Mode ..................................................... 43 External Zero Delay Mode .......................... …… 此处隐藏：18014字，全部文档内容请下载后查看。喜欢就下载吧 ……