IT6603 Datasheet v1 0

IT6603 Datasheet v1 0

IT6603Single-Link HDMI 1.3 ReceiverITE TECH. INC.http://www.77cn.com.cnFeb-2009 Rev:1.01/35

IT6603 Datasheet v1 0

IT6603 General DescriptionThe IT6603 is a single-link HDMI 1.3 receiver, fully compatible with HDMI 1.3, HDCP 1.2 and backward compatible to DVI 1.0 specifications. The IT6603 with its Deep Color capability (up to 36-bit) ensures robust reception of high-quality uncompressed video content, along with state-of-the-art uncompressed and compressed digital audio content such as DTS-HD and Dolby TrueHD in digital televisions and projectors. Aside from the various video output formats supported, the IT6603 also receives and provides up to 8 channels of I2S digital audio outputs, with sampling rate up to 192kHz and sample size up to 24 bits, facilitating direct connection to industry-standard low-cost audio DACs. Also, an S/PDIF output is provided to support up to compressed audio of 192kHz frame rate. Super Audio Compact Disc (SACD) is supported at up to 8 channels and 88.2kHz through DSD (Direct Stream Digital ports) ports. Each IT6603 comes preprogrammed with an unique HDCP key, in compliance with the HDCP 1.2 standard so as to provide secure transmission of high-definition content. Users of the IT6603 need not purchase any HDCP keys or ROMs.FeaturesSingle-link HDMI 1.3 receiver Compliant with HDMI 1.3a, HDCP 1.2 and DVI 1.0 specifications Supporting link speeds of up to 2.25Gbps (link clock rate of 225MHz). Video output interface supporting digital video standards such as: 24/30-bit RGB/YCbCr 4:4:4 16/20-bit YCbCr 4:2:2 8/10-bit YCbCr 4:2:2 (ITU BT-656) 24/30-bit double data rate interface (full bus width, pixel clock rate halved, clocked with both rising and falling edges) Input channel swap MSB/LSB swap Bi-direction Color Space Conversion (CSC) between RGB and YCbCr color spaces with programmable coefficients. Up/down sampling between YCbCr 4:4:4 and YCbCr 4:2:2 Dithering for conversion from 12-bit component to 10-bit/8-bit Digital audio output interface supporting up to four I2S interface supporting 8-channel audio, with sample rates of 32~192 kHz andFeb-2009 Rev:1.0 2/35http://www.77cn.com.cn

IT6603 Datasheet v1 0

IT6603sample sizes of 16~24 bits S/PDIF interface supporting PCM, Dolby Digital, DTS digital audio at up to 192kHz frame rate Optional support for 8-channel DSD audio up to 8 channels at 88.2kHz sample rate Support for high-bit-rate (HBR) audio such as DTS-HD and Dolby TrueHD through the four I2S interface or the S/PDIF interface, with frame rates as high as 768kHz automatic audio error detection for programmable soft mute, preventing annoying harsh output sound due to audio error or hot-unplug Auto-calibrated input termination impedance provides process-, voltage- and temperature-invariant matching to the input transmission lines. Integrated pre-programmed HDCP keys Intelligent, programmable power management 128-pin LQFP (14mm x 14mm) packagehttp://www.77cn.com.cnFeb-2009 Rev:1.03/35

IT6603 Datasheet v1 0

IT6603 Pin DiagramAVCC33 AVCC18 AVCC33 AVCC33 AVCC33 PVCC18 AVCC33 AVCC33 AVCC33 AVCC3334646362616059585756555453525150494847464544434241403938373635AVCC1833 32 31 30 29 28 27 26 25 24 23 22R0XCMR0XCPR0X2MR0X1MR0X0MR0X2PR0X1PR0X0POVSSAVSSAVSSAVSSAVSSREXTPVSSAVSSAVSSAVSSNCNCNCOVDD MUTE_DR3 DSD_DL3 SPDIF_DL2 IVSS IVDD I2S0_DL0 I2S1_DR1 I2S2_DL1 I2S3_DR2 WS_DR0 SCK_DCLK OVSS OVDD MCLK IVSS IVDD APVDD18 APVSS XTALOUT XTALIN XTALVDD33 REGVCC RSVDL SYSRSTN SCDT INT# OVDD PCADR IVSS IVDD QE3565 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 9192 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128AVSS R0PWR5V DDCSCL0 DDCSDA0 OVDD OVSS NC PCSCL PCSDA IVDD IVDD IVSS EVENODD VSYNC HSYNC DE OVDD OVSS QE2 QE3 IVDD IVSS QE4 QE5 QE6 QE7 OVDD PCLK OVSS QE8 QE9 QE10IT6603HDMI 1.3 RX LQFP-128 (Top View)21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1OVSSNote: 1. Pin51 must be connected with an external 500 SMD resistor to ground. This resistor serves to calibrate the on-chip termination impedances of all four pairs of high-speed serial links. 2. Pins marked with NC should be left unconnected.QE34QE33QE32OVSSOVDDQE31QE30QE29QE27QE26OVSSOVDDQE23QE22QE21QE20QE17QE16QE14QE11QE28OVDDQE15QE18QE19IVSSIVDDFigure 1. IT6603 pin diagramIVSSIVDDIVSSIVDDhttp://www.77cn.com.cnFeb-2009 Rev:1.04/35

IT6603 Datasheet v1 0

IT6603 Pin DescriptionDigital Video Onput PinsPin Name QE[35:26] QE[23:14] QE[11:2] Direction Output Description Digital Video Output Pins. Channel swap and MSB-LSB reversal are supported through register setting. Type LVTTL Pin No. 1-3, 7-10, 13-14, 96-99, 102-105, 108-109, 112-115, 118-121, 124-125, 128 PCLK DE HSYNC VSYNC EVENODD Output Output Output Output Output Output data clock. The backend controller should use the rising edge of PCLK to strobe QE[35:2] Data enable Horizontal sync. signal Vertical sync. signal Indicates whether the current field is Even or Odd for interlaced format LVTTL LVTTL LVTTL LVTTL 17 18 19 20 LVTTL 5Digital Audio Onput PinsPin Name XTALIN XTALOUT MCLK SCK_DCLK WS_DR0 I2S0_DL0 I2S1_DR1 I2S2_DL1 I2S3_DR2 SPDIF_DL2 MUTE_DR3 DSD_DL3 Direction Input Output Output Output Output Output Output Output Output Output Output Output Description Crystal clock input (for Audio PLL) Crystal clock output (for Audio PLL) Audio master clock I2S serial clock output, doubles as DSD clock I2S word select output, doubles as DSD Serial Right CH0 data output I2S serial data output, doubles as DSD Serial Left CH0 data output I2S serial data output, doubles as DSD Serial Right CH1 data output I2S serial data output, doubles as DSD Serial Left CH2 data output I2S serial data output, doubles as DSD Serial Right CH2 data output S/PDIF audio output, doubles as DSD Serial Left CH2 data output Mute output, doubles as DSD Serial Right CH3 data output DS …… 此处隐藏：24937字，全部文档内容请下载后查看。喜欢就下载吧 ……