Verilog HDL语言设计实验指导书(2004)(9)

s_to_p(.T1(T1),.data(data),.D_out(D_out),.DSC(DSC),.TAKE(TAKE),.ADD_101(ADD_101)); endmodule

测试模块源代码：

//-------------Top test file for sys.v ------------------ `timescale 1ns/100ps `include \module Top;

reg D_out,SEND,ESC,DSC,TAKE,ADD_100,ADD_101; reg[7:0] data_buf; wire [7:0] data; wire clk2;

assign data = (ADD_101) ? data_buf : 8'bz;

//data在sys中是inout型变量，ADD_101 //控制data是作为输入还是进行输出。

assign clk2 =DSC && TAKE; initial

begin

SEND = 0; ESC = 0; DSC = 1; TAKE = 1; ADD_100 = 1; ADD_101 = 1;

end

initial

begin

data_buf = 8'b10000001;

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