实验室温湿度监控系统的设计(1)(10)

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LCD1LM016LVSSVDDVEERSRWE7891011121314D0D1D2D3D4D5D6D7P1.74P1.656C1123RP111nF19XTAL1CRYSTAL18XTAL21nFX1U1C2S17C330PFRST9P0.0/AD0P0.1/AD1P0.2/AD2P0.3/AD3P0.4/AD4P0.5/AD5P0.6/AD6P0.7/AD7RESPACK-8393837363534333223456789R3U232SCKDATA>R110kP2.7293031PSENALEEA10k80.027.0%RHP2.0/A8P2.1/A9P2.2/A10P2.3/A11P2.4/A12P2.5/A13P2.6/A14P2.7/A15SHT112122232425262728癈

附录A温湿度监控系统仿真图

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S2S6AT89C51S4S5S9S13LS1SPEAKERS3S1123456P1.67P1.78P1.0/T2P1.1/T2EXP1.2P1.3P1.4P1.5P1.6P1.7P3.0/RXDP3.1/TXDP3.2/INT0P3.3/INT1P3.4/T0P3.5/T1P3.6/WRP3.7/RD10111213141516171C1+C41nF3C1-T1OUTR1IN1112109T1INR1OUTT2INR2OUTT1OUTR1INT2OUTR2INVS+VS-C2+C2-141378261uFS8S10S14S7U3S12S11S16S15C6P2.71kR2Q1PNPC745MAX232C51nF1uF

附录B外文文献及译文

Brief Introduction of AT89C51

The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash Programmable and Erasable Read Only Memory (PEROM) and 128 bytes RAM. The device is manufactured using Atmel’s high density nonvolatile memory technology and is compatible with the industry standard MCS-51? instruction set and pin out. The chip combines a versatile 8-bit CPU with Flash on a monolithic chip; the Atmel AT89C51 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications.

Features:

Compatible with MCS-51? Products

4K Bytes of In-System Reprogrammable Flash Memory Endurance: 1,000 Write/Erase Cycles Fully Static Operation: 0 Hz to 24 MHz Three-Level Program Memory Lock 128 x 8-Bit Internal RAM 32 Programmable I/O Lines Two 16-Bit Timer/Counters Six Interrupt Sources

Programmable Serial Channel

Low Power Idle and Power Down Modes

The AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.

Pin Description:

VCC Supply voltage. GND Ground. Port 0

Port 0 is an 8-bit open drain bidirectional I/O port. As an output port each pin can sink eight TTL inputs. When is written to port 0 pins, the pins can be used as high impedance inputs.

Port 0 may also be configured to be the multiplexed low order address/data bus

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during accesses to external program and data memory. In this mode P0 has internal pull-ups.

Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pull-ups are required during program verification.

Port 1

Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 1 also receives the low-order address bytes during Flash programming and verification.

Port 2

Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that uses 16-bit addresses (MOVX @ DPTR). In this application it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that uses 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.

Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.

Port 3

Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups. Port 3 also serves the functions of various special features of the AT89C51 as listed below: Port 3 also receives some control signals for Flash programming and verification.

RST

Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.

ALE/PROG

Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG)

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