AT89C51单片机 外文翻译(2)

附件2：外文原文（复印件）

Features

Compatible with MCS-51? Products、4K Bytes of In-System Reprogrammable Flash Memory、Endurance: 1,000 Write/Erase Cycles、Fully Static Operation: 0 Hz to 24 MHz、Three-level Program Memory Lock、128 x 8-bit Internal RAM、 32 Programmable I/O Lines、Two 16-bit Timer/Counters、Six Interrupt Sources、 Programmable Serial Channel、Low-power Idle and Power-down Modes.

Description

The AT89C51 is a low-power,high-performance CMOS 8-bit microcosmputer with 4K bytes of Flash programmable and erasable read only memory(PEROM).The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with industry-standard MS-51 instruction set and pinout. The on-chipFlash allows the program memory to be reprogrammed in-system or by a conventionalnonvolatile memory programmer. By combining a versatile 8-bit CPU with Flashon a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which providesa highly-flexible and cost-effective solution to many embedded control applications.

Pin Configurations

Block Diagram

The AT89C51 provides the following standard features: 4Kbytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bittimer/counters, a five vector two-level interrupt architecture ,a full duplex serial port, on-chip oscillator and clock circuitry .In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters serial port and interrupt system to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset

Pin Description VCC

Supply voltage GND Ground. Port 0

Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port,

each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs.

Port 0 may also be configured to be the multiplexed low order addess/ data bus during accesses to external program and data memory. In this mode P0 has internal pullups.

Port 0 also receives the code bytes during Flash programming ,and outputs the code bytes during program verification. External pullups are required during program verification.

Port 1

Port 1 is an 8-bit bi-directional I/O port with internal pullups .The Port 1 output buffers can sink/source four TTL inputs When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs ,Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.

Port 1 also receives the low-order address bytes during Flash programming and verification.

Port 2

Port 2 is an 8-bit bi-directional I/O port with internal pullups .The Port 2 output buffers can sink/source four TTL inputs .When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups.

Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.

Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.

Port 3

Port 3 is an 8-bit bi-directional I/O port with internal pullups .The Port 3 output buffers can sink/source four TTL inputs .When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs ,Port 3 pins that are externally being pulled low will source current (IIL) because of the pullupsn .

Port 3 also serves the functions of various special features of the AT89C51 as listed below:

Port 3 also receives some control signals for Flash programming and verification.

RST

Rest input, A high on this pin for two machine cycles while the oscillator is running resets the device

ALE/PROG

Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming .

In normal operation ALE is emitted at a constant rate of 1/6the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory .

If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has

no effect if the microcontroller is in external execution mode.

PSEN

Program Store Enable is the read strobe to external program memory . When the AT89C51 is executing code from external program memory , PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. EA/VPP

External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.

EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash p …… 此处隐藏：4480字，全部文档内容请下载后查看。喜欢就下载吧 ……