EL1881CSZ-T13中文资料

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®

EL1881

Data Sheet

October 20, 2004

FN7018.1

Sync Separator, Low Power

The EL1881 video sync separator is manufactured using Elantec’s high performance analog CMOS process. This device extracts sync timing information from both standard and non-standard video input. It provides composite sync, vertical sync, burst/back porch timing, and odd/even field detection. Fixed 70mV sync tip slicing provides sync edge detection when the video input level is between 0.5VP-P and -2VP-P (sync tip amplitude 143mV to 572mV). A single external resistor sets all internal timing to adjust for various video standards. The composite sync output follows video in sync pulses and a vertical sync pulse is output on the rising edge of the first vertical serration following the vertical pre-equalizing string. For non-standard vertical inputs, a default vertical pulse is output when the vertical signal stays low for longer than the vertical sync default delay time. The

odd/even output indicates field polarity detected during the vertical blanking interval. The EL1881 is plug-in compatible with the industry-standard LM1881 and can be substituted for that part in 5V applications with lower required supply current.

The EL1881 is available in the 8-pin PDIP and SO packages and is specified for operation over the full -40°C to +85°C temperature range.

Features

NTSC, PAL, SECAM, non-standard video sync separation Fixed 70mV slicing of video input levels from 0.5VP-P to 2VP-P Low supply current - 1.5mA typ. Single +5V supply

Composite, vertical sync output Odd/even field output Burst/back porch output

Available in 8-pin PDIP and SO packages Pb-free available

Applications

Video amplifiers PCMCIA applications A/Ddrivers Line drivers Portable computers High-speed communications RGB applications

Ordering Information

PART NUMBEREL1881CNEL1881CSEL1881CS-T7EL1881CS-T13EL1881CSZ

(See Note)EL1881CSZ-T7(See Note)EL1881CSZ-T13(See Note)

PACKAGE8-Pin PDIP8-Pin SO8-Pin SO8-Pin SO8-Pin SO(Pb-free)8-Pin SO(Pb-free)8-Pin SO(Pb-free)

TAPE & REEL

--7”13”-7”13”

PKG. DWG. #MDP0031MDP0027MDP0027MDP0027MDP0027MDP0027MDP0027

Broadcast equipment Active filtering

Demo Board

A dedicated demo board is available.

Pinout

EL1881 (8-PIN PDIP, SO)TOP VIEW

COMPOSITE SYNC OUT1COMPOSITE VIDEO IN2VERTICAL SYNC OUT3

GND

4

8

VDD 5V

7ODD/EVEN OUTPUT6

RSET

NOTE:Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C.

5BUST/BACK PORCH OUTPUT

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EL1881C

Absolute Maximum Ratings (TA = 25°C)

VCC Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7VStorage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°CPin Voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VCC +0.5V

Operating Ambient Temperature Range . . . . . . . . . .-40°C to +85°COperating Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150°CPower Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400mW

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of thedevice at these or any other conditions above those indicated in the operational sections of this specification is not implied.

IMPORTANT NOTE:All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all testsare at the specified temperature and are pulsed tests, therefore: TJ = TC = TA

DC Electrical Specifications

PARAMETER

IDD, QuiescentClamp Voltage

Clamp Discharge CurrentClamp Charge CurrentRSET Pin Reference VoltageVOL Output Low VoltageVOH Output High Voltage

VDD = 5V, TA = 25°C, RSET = 681k , unless otherwise specified.

DESCRIPTION

VDD = 5V

Pin 2, ILOAD = -100µAPin 2 = 2VPin 2 = 1VPin 6IOL = 1.6mAIOH = -40µAIOH = -1.6mA

43MIN0.751.356-1.31.1

TYP1.51.512-11.220.244.84.6

MAX31.65160.71.350.5

UNITmAVµAmAVVV

Dynamic Specifications

PARAMETER

Comp Sync Prop Delay, tCSVertical Sync Width, tVS

Vertical Sync Default Delay, tVSDBurst/Back Porch Delay, tBDBurst/Back Porch Width, tBInput Dynamic RangeSlice Level

See Figure 2

Normal or Default Trigger, 50%-50%See Figure 3See Figure 2See Figure 2

Video Input Amplitude to Maintain 50% Slice SpecVSLICE/VCLAMP

DESCRIPTION

MIN20190351202.50.555

70TYP35230622003.5

MAX75300853004.5285

UNITnsµsµsnsµsVP-PmV

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EL1881C

Pin Descriptions

PIN NUMBER

12345678

NOTE:

1.RSET must be a 1% resistor

PIN NAMEComposite Sync Out

Composite Video In

Vertical Sync OutGND

Burst/Back Porch OutputRSET (Note 1)Odd/Even OutputVDD 5V

PIN FUNCTION

Composite sync pulse output; sync pulses start on a falling edge and end on a rising edgeAC coupled composite video input; sync tip must be at the lowest potential (positive picture phase)Vertical sync pulse output; the falling edge of vert sync is the start of the vertical periodSupply ground

Burst/back porch output; low during burst portion of composite video

An external resistor to ground sets all intern …… 此处隐藏：12392字，全部文档内容请下载后查看。喜欢就下载吧 ……