FPGA可编程逻辑器件芯片EP1S30F780C8中文规格书

Stratix II GX Device Handbook, Volume 1Figure 2–16.Receiver PLL and CRU

The receiver PLLs and CRUs can support frequencies up to 6.375 Gbps. The input clock frequency is limited to the full clock range of 50 to 622MHz but only when using REFCLK0 or REFCLK1. An optional

RX_PLL_LOCKED port is available to indicate whether the PLL is locked to the reference clock. The receiver PLL has a programmable loop bandwidth which can be set to low, medium, or high. The Quartus II software can statically set the loop bandwidth parameter.

All the parameters listed are programmable in the Quartus II software. The receiver PLL has the following features:

■

Operates from 600 Mbps to 6.375 Gbps.■

Uses a reference clock between 50 MHz and 622.08 MHz.■

Programmable bandwidth settings: low, medium, and high.■

Programmable rx_locktorefclk (forces the receiver PLL to lock to the reference clock) and rx_locktodata (forces the receiver PLL to lock to the data).■

The voltage-controlled oscillator (VCO) operates at half rate and has two modes. These modes are for low or high frequency operation and provide optimized phase-noise performance.■

Programmable frequency multiplication W of 1, 4, 5, 8, 10, 16, 20, and 25.Not all settings are supported for any particular frequency.■Two lock indication signals are provided. They are found in PFD

mode (lock-to-reference clock), and PD (lock-to-data).

Stratix II GX Architecture This module detects word boundaries for the 8B/10B-based protocols, SONET, 16-bit, and 20-bit proprietary protocols. This module is also used to align to specific programmable patterns in PRBS7/23 test mode. Pattern Detection

The programmable pattern detection logic can be programmed to align word boundaries using a single 7-, 8-, 10-, 16-, 20, or 32-bit pattern. The pattern detector can either do an exact match, or match the exact pattern and the complement of a given pattern. Once the programmed pattern is found, the data stream is aligned to have the pattern on the LSB portion of the data output bus.

XAUI, GIGE, PCI Express, and Serial RapidIO standards have embedded state machines for symbol boundary synchronization. These standards use K28.5 as their 10-bit programmed comma pattern. Each of these standards uses different algorithms before signaling symbol boundary acquisition to the FPGA.

The pattern detection logic searches from the LSB to the most significant bit (MSB). If multiple patterns are found within the search window, the pattern in the lower portion of the data stream (corresponding to the pattern received earlier) is aligned and the rest of the matching patterns are ignored.

Once a pattern is detected and the data bus is aligned, the word boundary is locked. The two detection status signals (rx_syncstatus and

rx_patterndetect) indicate that an alignment is complete.

Figure2–18 is a block diagram of the word aligner.

Figure2–18.Word Aligner

Stratix II GX Device Handbook, Volume 1

Transceivers

Stratix II GX Device Handbook, Volume 1

Stratix II GX Architecture

Stratix II GX Device Handbook, Volume 1

Transceivers

When the FIFO pointers initialize, the receiver domain clock must remain

phase locked to receiver FPGA clock.

After resetting the receiver FIFO buffer, writing to the receiver FIFO

buffer begins and continues on each parallel clock. The phase

compensation FIFO buffer is eight words deep for PIPE mode and four

words deep for all other modes.

Loopback Modes

The Stratix II GX transceiver has built-in loopback modes for debugging

and testing. The loopback modes are configured in the Stratix II GX

ALT2GXB megafunction in the Quartus II software. The available

loopback modes are:

■Serial loopback

■Parallel loopback

■Reverse serial loopback

■Reverse serial loopback (pre-CDR)

■PCI Express PIPE reverse parallel loopback (available only in PIPE

mode)

Serial Loopback

The serial loopback mode exercises all the transceiver logic, except for the

input buffer. Serial loopback is available for all non-PIPE modes. The

loopback function is dynamically enabled through the

rx_seriallpbken port on a channel-by-channel basis.

In serial loopback mode, the data on the transmit side is sent by the PLD.

A separate mode is available in the ALT2GX

B megafunction under Basic

protocol mode, in which PRBS data is generated and verified internally in

the transceiver. The PRBS patterns available in this mode are shown in

Table2–10.

Table2–10 shows the BIST data output and verifier alignment pattern.

Table2–10.BIST Data Output and Verifier Alignment Pattern

Pattern Polynomial

Parallel Data Width

8-Bit10-Bit16-Bit20-Bit

PRBS-7×7 + ×6 + 1v

PRBS-10×10 + ×7 + 1v

Stratix II GX Device Handbook, Volume 1