M37544RSS中文资料

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元器件交易网http://doc.guandang.net

元器件交易网http://doc.guandang.net

元器件交易网http://doc.guandang.net

元器件交易网http://doc.guandang.net

元器件交易网http://doc.guandang.net

7544 Group

PIN DESCRIPTION

Table 1 Pin description

PinNameVcc, VssVREFCNVssRESETXINXOUT

Power source

Function

Apply voltage of 4.0 to 5.5 V to Vcc, and 0 V to Vss.

Function expect a port function

Analog reference Reference voltage input pin for A/D convertervoltageCNVss

Reset inputClock inputClock output

Chip operating mode control pin, which is always connected to Vss. Reset input pin for active “L”

Input and output pins for main clock generating circuit

Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins. For using RC oscillator, short between the XIN and XOUT pins, and connect the capacitor and resistor. If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. When the on-chip oscillator is selected as the main clock, connect XIN pin to VCC and leave XOUT open. 8-bit I/O port.

I/O direction register allows each pin to be inpidually pro-grammed as either input or output. CMOS compatible input level CMOS 3-state output structure

P0 can output a large current for driving LED.

Whether a built-in pull-up resistor is to be used or not can be de-termined by program.

Key-input (key-on wake upinterrupt input) pins

Timer X and timer A functionpin

P00/CNTR1P01P02

P03/TXOUTP04–P07

I/O port P0

P10/RxDP11/TxD

CLKP12/S____P13/SRDY

I/O port P1

5-bit I/O port

I/O direction register allows each pin to be inpidually pro-grammed as either input or output. CMOS compatible input level CMOS 3-state output structure

CMOS/TTL level can be switched for P10 and P12 6-bit I/O port having almost the same function as P0 CMOS compatible input level CMOS 3-state output structure 6-bit I/O port

Serial I/O function pin

P14/CNTR0

P20/AN0–P25/AN5I/O port P2

Timer X function pin Input pins for A/D converter

P30–P33I/O port P3

I/O direction register allows each pin to be inpidually programmed as either input or output. CMOS compatible input level (CMOS/TTL level can be switched for P34 and P37). CMOS 3-state output structure

P3 can output a large current for driving LED.

P34/INT1P37/INT0

Whether a built-in pull-up resistor is to be used or not can be de-termined by program.

Interrupt input pins

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7544 Group

Processor status register (PS)

The processor status register is an 8-bit register consisting offlags which indicate the status of the processor after an arithmeticoperation. Branch operations can be performed by testing theCarry (C) flag, Zero (Z) flag, Overflow (V) flag, or the Negative (N)flag. In decimal mode, the Z, V, N flags are not valid.

After reset, the Interrupt disable (I) flag is set to “1”, but all otherflags are undefined. Since the Index X mode (T) and Decimalmode (D) flags directly affect arithmetic operations, they shouldbe initialized in the beginning of a program.

(1) Carry flag (C)

The C flag contains a carry or borrow generated by the arithmeticlogic unit (ALU) immediately after an arithmetic operation. It canalso be changed by a shift or rotate instruction.

(2) Zero flag (Z)

The Z flag is set if the result of an immediate arithmetic operationor a data transfer is “0”, and cleared if the result is anything otherthan “0”.

(3) Interrupt disable flag (I)

The I flag disables all interrupts except for the interrupt generatedby the BRK instruction. Interrupts are disabled when the I flag is“1”.

When an interrupt occurs, this flag is automatically set to “1” toprevent other interrupts from interfering until the current interruptis serviced.

(4) Decimal mode flag (D)

The D flag determines whether additions and subtractions are ex-ecuted in binary or decimal. Binary arithmetic is executed whenthis flag is “0”; decimal arithmetic is executed when it is “1”.

Decimal correction is automatic in decimal mode. Only the ADCand SBC instructions can be used for decimal arithmetic.

(5) Break flag (B)

The B flag is used to indicate that the current interrupt was gener-ated by the BRK instruction. The BRK flag in the processor statusregister is always “0”. When the BRK instruction is used to gener-ate an interrupt, the processor status register is pushed onto thestack with the break flag set to “1”. The saved processor status isthe only place where the break flag is ever set.

(6) Index X mode flag (T)

When the T flag is “0”, arithmetic operations are performed be-tween accumulator and memory, e.g. the results of an operationbetween two memory locations is stored in the accumulator. Whenthe T flag is “1”, direct arithmetic operations and direct data trans-fers are enabled between memory locations, i.e. between memoryand memory, memory and I/O, and I/O and I/O. In this case, theresult of an arithmetic operation performed on data in memory lo-cation 1 and memory location 2 is stored in memory location 1.The address of memory location 1 is specified by index register X,and the address of memory location 2 is specified by normal ad-dressing modes.

(7) Overflow flag (V)

The V flag is used during the addition or subtraction of one byte ofsigned data. It is set if the result exceeds +127 to -128. When theBIT instruction is executed, bit 6 of the memory location operatedon by the BIT inst …… 此处隐藏：5043字，全部文档内容请下载后查看。喜欢就下载吧 ……