EDI2GG46464V95D中文资料

元器件交易网http://doc.guandang.net

EDI2GG46464V

4x64Kx64, 3.3V Synchronous SRAM CARD EDGE DIMM

FEATURES

s4x64Kx64 Synchronous

sAccess Speed(s): TKHQV = 9.5, 10, 11,12, 15nssFlow-Through Architecture

sClock Controlled Registered Bank Enables (E1\,E2\, E3\, E4\)sClock Controlled Registered Address

sClock Controlled Registered Global Write (GW\)sAysnchronous Output Enable (G\)sInternally self-timed Write+sGold Lead Finishs3.3V ±10%, -5% OperationsCommon Data I/O

sHigh Capacitance (30pF) drive, at rated Access SpeedsSingle total array ClocksMultiple Vcc and Vss

The EDI2GG46464VxxD is a Synchronous SRAM, 60 positionDual Key; Card Edge DIMM (120 contacts) Module, organized as4x64Kx64. The Module contains eight (8) Synchronous BurstRam Devices, packaged in the industry standard JEDEC 14mmx20mmTQFP placed on a Multilayer FR4 Substrate. The module architectureis defined as a Synchronous Only, Flow-Through, Early Writedevice. This Module provides high performance, ultra fast accesstimes at a cost per bit benefit over BiCMOS Asynchronous devices.As well as improved cost per bit, the use of Synchronous orSynchronous burst devices or modules can ease the memorysubsystem design by reducing or easing the memory controllerrequirement.

Synchronous operations are in relation to an externally suppliedclock, registered address, registered global write, registered enablesas well as an Asynchronous Output enable. All Read and Writeoperations are performed in Quad Words (64 bit operations).Write cycles are internally self timed and are initiated by a risingclock edge. This feature relieves the designer the task of developingexternal pulse width circuitry.

February 1999 Rev. 2ECO# 10858

1

White Electronic Designs Corporation (508) 366-5151 http://doc.guandang.net

元器件交易网http://doc.guandang.net

EDI2GG46464V

PIN CONFIGURATION

VSSA0A1A2A3VCCA4A5A6A7VSSA8VSSCLKVSSE4\VCCE3\G\VSSDQ0DQ1DQ2DQ3VCCDQ8DQ9DQ10DQ11VSSDQ16DQ17DQ18DQ19VCCDQ24DQ25DQ26DQ27VSSDQ32DQ33DQ34DQ35VCCDQ40DQ41DQ42DQ43VSSDQ48DQ49DQ50DQ51VCCDQ56DQ57DQ58DQ59VSS

13579111315171921232527293133353739414345474951246810121416182022242628303234363840424446485052VSSNCA15A14A13VCCA12A11A10A9VSSRFUVSSNCVSSE2\VCCE1\GW\VSSDQ7DQ6DQ5DQ4VCCDQ15

5355575961636567697173757779818385878991939597991011031051071091111131151171195456586062646668707274767880828486889092949698100102104106108110112114116118120DQ14DQ13DQ12VSSDQ23DQ22DQ21DQ20VCCDQ31DQ30DQ29DQ28VSSDQ39DQ38DQ37DQ36VCCDQ47DQ46DQ45DQ44VSSDQ55DQ54DQ53DQ52VCCDQ63DQ62DQ61DQ60VSS

White Electronic Designs Corporation (508) 366-5151 http://doc.guandang.net

2

元器件交易网http://doc.guandang.net

EDI2GG46464V

FUNCTIONAL BLOCK DIAGRAM

A0-A15GW\G\

PIN NAMES

DQ0-63A0-15

DQ

DQ

Input/Output BusAddress BusSynchronous Bank

EnablesArray ClockSynchronous GlobalWrite Enable3.3V Power Supply

GroundNo Connect

GW\

E1\

64Kx32

GW\G\E\

64Kx32

E1\, E2\,E3\, E4\CLKGW\G\

G\

E\CLK

CLK

E2\

64Kx32

GW\G\E\

GW\G\E\

64Kx32

DQDQ

VccVssNC

CLKCLK

GW\

E3\

G\E\

64Kx32

GW\G\E\

CLKCLK

64Kx32

GW\G\E\

GW\G\E\

CLKCLK

E4\

DQ0-DQ31DQ32-DQ63

CLK

64Kx32

DQ

64Kx32

DQDQ

DQ

PIN DESCRIPTIONS

DIMM Pins3, 5, 7, 9, 13, 15,17, 19, 23, 20, 18,16, 14, 10, 8, 6

382736, 32,35, 3137VariousVariousVarious

SymbolA0-15

TypeInputSynchronousInputSynchronousInputSynchronousInputSynchronous

InputInput/OutputSupplyGround

Description

Addresses: These inputs are registered and must meet the setup and hold times around the rising edge of CLK.The burst counter generates internal addresses associated with A0 and A1, during burst and wait cycle.Global Write: This active LOW input allows a full 72-bit WRITE to occur independent of the BWE\ and BWx\ linesand must meet the setup and hold times around the rising edge of CLK.

Clock: This signal registers the addresses, data, chip enables, write control and burst control inputs on its risingedge. All synchronous inputs must meet setup and hold times around the clock’s rising edge.Bank Enables: These active LOW inputs are used to enable each inpidual bank and to gate ADSP\.Output Enable: This active LOW asynchronous input enables the data output drivers.

Data Inputs/Outputs: First byte is DQ0-7, second byte is DQ8-15, third byte is DQ16-23, fourth byte is DQ24-31, fifth byte is DQ32-39, sixth byte is DQ40-47, seventh byte is DQ48-55 and the eight byte is DQ56-64.Core power supply: +3.3V -5%/+10%Ground

GW\CLKE1\, E2\E3\, E4\G\DQ0-63VccVss

3

White Electronic Designs Corporation (508) 366-5151 http://doc.guandang.net

元器件交易网http://doc.guandang.net

EDI2GG46464V

SYNCHRONOUS ONLY - TRUTH TABLE

Operation

Synchronous Write-Bank 1Synchronous Read-Bank 1Synchronous Write-Bank 2Synchronous Read-Bank 2Synchronous Write-Bank 3Synchronous Read-Bank 3Synchronous Write-Bank 4Synchronous Read-Bank 4Snooze Mode

E1\LLHHHHHHX

E2\HHLLHHHHX

E3\HHHHLLHHX

E4\HHHHHHLLX

GW\LHLHLHLHX

G\HL

HLHLHLX

CLK↑↑↑↑↑↑↑↑X

DQHigh-Z High-ZHigh-ZHigh-ZHigh-Z

ABSOLUTE MAXIMUM RATINGS*

Voltage on Vcc Relative to VssVin

Storage Temperature

Operating Temperature (Commercial)Operating Temperature (Industrial)Short Circuit Output Current

-0.5V to +4.6V-0.5V to Vcc +0.5V-55°C to +125°C0°C to +70°C-40°C to +85°C

20mA

RECOMMENDED DC OPERATING CONDITIONS

ParameterSupply VoltageSupply VoltageInput HighInput LowInput LeakageOutput LeakageOutput HighIOH = -4mAOutput LowIOL = 8mA

SymVCCVSSVIHVILILiILoVOHVOL…… 此处隐藏：5815字，全部文档内容请下载后查看。喜欢就下载吧 ……