数字集成电路：电路系统与设计(第二版) (2)

数字集成电路(设计透视)

41C H A P T E R

2

T H E M A N U F A C T U R I N G P R O C E S S n

Overview of manufacturing process

n

Design rules

n

IC packaging

Future Trends in Integrated Circuit Technology

2.1

Introduction 2.2Manufacturing CMOS Integrated Circuits

2.2.1

The Silicon Wafer 2.2.2

Photolithography 2.2.3

Some Recurring Process Steps 2.2.4Simplified CMOS Process Flow 2.3

Design Rules — The Contract between Designer and Process Engineer 2.4Packaging Integrated Circuits

2.4.1

Package Materials 2.4.2

Interconnect Levels 2.4.3Thermal Considerations in Packaging

2.5Perspective — Trends in Process Technology 2.5.1Short-Term Developments 2.5.2In the Longer Term 2.6

Summary

数字集成电路(设计透视)

42THE MANUFACTURING PROCESS Chapter 2 2.1Introduction

Most digital designers will never be confronted with the details of the manufacturing pro-cess that lies at the core of the semiconductor revolution. Yet, some insight in the steps that lead to an operational silicon chip comes in quite handy in understanding the physical constraints that are imposed on a designer of an integrated circuit, as well as the impact of the fabrication process on issues such as cost.

In this chapter, we briefly describe the steps and techniques used in a modern inte-grated circuit manufacturing process. It is not our aim to present a detailed description of the fabrication technology, which easily deserves a complete course [Plummer00]. Rather we aim at presenting the general outline of the flow and the interaction between the vari-ous steps. We learn that a set of optical masks forms the central interface between the intrinsics of the manufacturing process and the design that the user wants to see trans-ferred to the silicon fabric. The masks define the patterns that, when transcribed onto the different layers of the semiconductor material, form the elements of the electronic devices and the interconnecting wires. As such, these patterns have to adhere to some constraints in terms of minimum width and separation if the resulting circuit is to be fully functional.

This collection of constraints is called the design rule set, and acts as the contract between the circuit designer and the process engineer. If the designer adheres to these rules, he gets

a guarantee that his circuit will be manufacturable. An overview of the common design

rules, encountered in modern CMOS processes, will be given. Finally, an overview is given of the IC packaging options. The package forms the interface between the circuit implemented on the silicon die and the outside world, and as such has a major impact on the performance, reliability, longevity, and cost of the integrated circuit.

2.2Manufacturing CMOS Integrated Circuits

A simplified cross section of a typical CMOS inverter is shown in Figure 2.1. The CMOS

process requires that both n-channel (NMOS) and p-channel (PMOS) transistors be built in the same silicon material. To accommodate both types of devices, special regions called wells must be created in which the semiconductor material is opposite to the type of the channel. A PMOS transistor has to be created in either an n-type substrate or an n-well, while an NMOS device resides in either a p-type substrate or a p-well. The cross section

Figure 2.1Cross section of an n-well CMOS process.

数字集成电路(设计透视)

Section 2.2Manufacturing CMOS Integrated Circuits 43

shown in Figure 2.1 features an n -well CMOS process, where the NMOS transistors are implemented in the p -doped substrate, and the PMOS devices are located in the n -well.Modern processes are increasingly using a dual-well approach that uses both n - and p -wells, grown on top on a epitaxial layer, as shown in Figure 2.2. We will restrict the remainder of this discussion to the latter process (without loss of generality).

The CMOS process requires a large number of steps, each of which consists of a

sequence of basic operations. A number of these steps and/or operations are executed very repetitively in the course of the manufacturing process. Rather than ping directly into a description of the overall process flow, we first discuss the starting material followed by a detailed perspective on some of the most-often recurring operations.

2.2.1The Silicon Wafer

The base material for the manufacturing process comes

in the form of a single-crystalline, lightly doped wafer .

These wafers have typical diameters between 4 and 12

inches (10 and 30 cm, respectively) and a thickness of

at most 1 mm, and are obtained by cutting a single-

crystal ingot into thin slices (Figure 2.3). A starting

wafer of the p --type might be doped around the levels

of 2 × 1021 impurities/m 3. Often, the surface of the

wafer is doped more heavily, and a single crystal epi-

taxial layer of the opposite type is grown over the sur-

face before the wafers are handed to the processing

company. One important metric is the defect density of

the base material. High defect densities lead to a larger

fraction of non-functional circuits, and consequently an

increase in cost of the final product.Figure 2.2Cross section of modern dual-well CMOS process.

Figure 2.3Single-crystal ingot and

sliced wafers (from [Fullman99]).

数字集成电路(设计透视)

44THE MANUFACTURING PROCESS Chapter 2

2.2.2Photolithography

In each processing step, a certain area on the chip is masked out using the appropriate opti-cal mask so that a desired processing step can be selectively applied to the remaining regions. The processing step can be any of a wide range of tasks including oxidation, etch-ing, metal and polysilicon deposition, and ion implantation …… 此处隐藏：33381字，全部文档内容请下载后查看。喜欢就下载吧 ……