ad9954编程注意事项和寄存器介绍(5)

CFR1<21>=1。线性扫描no-dwell功能被激活。如果No-Dwell模式被激活，当扫描完成时，相位累加器被清零。相位累加器保持清零直到其他扫频初始化经过一个IO更新或者在断面改变 CFR1<2>: Linear Sweep No-Dwell Bit

If CFR1<21> is clear, this bit is a don’t care (ignored). CFR1<2> = 0 (default). The linear sweep no-dwell function is inactive. If the no-dwell mode is inactive when the sweep completes, sweeping does not restart until an I/O update or change in profile initiates another sweep as previously described. The output frequency holds at the final value in the sweep.

CFR1<2> = 1. The linear sweep no-dwell function is active. If the no-dwell mode is active when the sweep completes, the phase accumulator is cleared. The phase accumulator remains cleared until another sweep is initiated via an I/O update input or change in profile.

CFR1<1>: SYNC_CLK 禁止位

CFR1<1> = 0 (默认)。SYNC_CLK被激活。

CFR1<1> =1。SYNC_CLK引脚呈现一个静态逻辑0状态为了减小数字电路产生的噪音。同步电路保持内部激活，为了保留器件标准时间。 CFR1<1>: SYNC_CLK Disable Bit

CFR1<1> = 0 (default). The SYNC_CLK pin is active.

CFR1<1> = 1. The SYNC_CLK pin assumes a static Logic 0 state to minimize noise generated by the digital circuitry. The synchronization circuitry remains active internally to maintain normal device timing.

CFR1<0>:不被使用，待清零 CFR1<0>: Not Used, Leave Clear

控制功能寄存器NO2(CFR2)

CFR2被使用控制AD9954多种功能，特征，和模式，首先关系到芯片模拟部分。

Control Function Register No. 2 (CFR2)

The CFR2 is used to control the various functions, features, and modes of the AD9954, primarily related to the analog sections of the chip.

CFR2<23:12>:不被使用，待清零 CFR2<23:12>: Not Used, Leave Clear

CFR2<11>:高速同步使能位

CFR2<11> = 0（默认）。高速同步使放大关闭。

CFR2<11> = 1. 高速同步使放大开。这位需要被设置，当使用自动同步特性在SYNC_CLK > 50 MHz(SYSCLK > 200 MSPS). CFR2<11>: High Speed Sync Enable Bit

CFR2<11> = 0 (default). The high speed sync enhancement is off. CFR2<11> = 1. The high speed sync enhancement is on. This bit should be set when using the autosynchronization feature for SYNC_CLK > 50 MHz (SYSCLK > 200 MSPS).

CFR2<10>:硬件手动同步使能位

CFR2<10> = 0（默认）。硬件手动同步功能关闭。

CFR2<10> = 1。硬件手动同步功能激活。当这位被设置，SYNC_IN管脚上升沿引起器件优先SYNC_CLK上升沿通过一个REFCLK周期。这位不自身清零。

CFR2<10>: Hardware Manual Sync Enable Bit

CFR2<10> = 0 (default). The hardware manual sync function is off.

CFR2<10> = 1. The hardware manual sync function is enabled. While this bit is set, a rising edge on the SYNC_IN pin causes the device to advance the SYNC_CLK rising edge by one REFCLK cycle. This bit does not self-clear.

CFR2<9>:晶体输出使能位

CFR2<9> = 0（默认）。晶体输出管脚未被激活。

CFR2<9> = 1。晶体输出管脚被激活。石英晶体振荡器电路输出驱动晶体输出关脚，这些可以为附加装置用作基准频率。 CFR2<9>: CRYSTAL OUT Enable Bit

CFR2<9> = 0 (default). The CRYSTAL OUT pin is inactive. CFR2<9> = 1. The CRYSTAL OUT pin is active. The crystal oscillator circuitry output drives the CRYSTAL OUT pin, which can be used as a reference frequency for additional devices.

CFR2<8>:不被使用，待清零 CFR2<8>: Not Used, Leave Clear

CFR2<7:3>:基准时钟增益控制位

这5位控制时钟乘法器（PLL）的输出增益值。参看时钟乘法器部分。 CFR2<7:3>: Reference Clock Multiplier Control Bits This 5-bit word controls the multiplier value out of the clock-multiplier (PLL) block. See the Clock Multiplier section for more details.

CFR2<2>:VCO范围控制位

CFR2<2> = 0（默认），VCO操作在100MHz和250MHz。 CFR2<2> = 1。VCO操作在250MHz和400MHz.

CFR2<2>: VCO Range Control Bit

CFR2<2> = 0 (default), VCO operates between 100 MHz and 250 MHz. CFR2<2> = 1, VCO operates between 250 MHz and 400 MHz.

CFR2<1:0>:泵源电流控制位

这一位被用做控制泵源电流整定值。默认设置，CFR2<1:0>，设置泵源电流在默认的75μA。对应每位增加，25μA电流被加到泵源电流。01=100μA，10=125μA，11=150μA。

CFR2<1:0>: Charge Pump Current Control Bits

These bits are used to control the current setting on the charge pump. The default setting, CFR2<1:0>, sets the charge pump current to the default value of 75 μA. For each bit added, 25 μA of current is added to the charge pump current: 01 = 100 μA, 10 = 125 μA, and 11 = 150 μA.

PDF 31页右下 其他寄存器介绍

幅度系数设置Amplitude Scale Factor (ASF)

ASF包括2bit的自动倾斜速率值（auto ramp rate speed value ）和14bit幅度系数值（Amplitude Scale Factor）在OSK（不懂这个术语，有知道的通知我谢谢）中使用。在自动OSK模式下，14bit和15bit 用来设置每次振幅增减的步进。Bit13到bit0 是用来设置内部幅度乘法