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ad9954编程注意事项和寄存器介绍(3)

来源:网络收集 时间:2025-04-28
导读: These bits cause the profile bits to be ignored when the RAM is being used and puts the AD9954 into an automatic profile loop sequence that allows the user to implement a frequency/phase composite sw

These bits cause the profile bits to be ignored when the RAM is being used and puts the AD9954 into an automatic profile loop sequence that allows the user to implement a frequency/phase composite sweep that runs without external inputs. See the Internal Profile Control section for more details.

CFR1<26>:装入在振幅斜坡速率控制位

CFR1<26> = 0(默认)。振幅斜坡速率定时器被装载只有在超时上(时钟==1);它不被装由于IO更新输入信号。

CFR1<26> =1。振幅斜坡速率定时器被装载时钟上升延时(时钟==1),或者在IO更新输入信号的时候。

CFR1<26>: Load Amplitude Ramp Rate Control Bit

CFR1<26> = 0 (default). The amplitude ramp rate timer is loaded only upon timeout (timer == 1); it is not loaded due to an I/O update input signal.

CFR1<26> = 1. The amplitude ramp rate timer is loaded upon either timeout (timer == 1) or at the time of an I/O update input signal.

CFR1<25>: Shaped On-Off Keying 使能位

CFR1<25>=0(默认)。Shaped on-off keying 被旁路。 CFR1<25>=1. Shaped on-off keying 被允许。参阅CFR<24>。 CFR1<25>: Shaped On-Off Keying Enable Bit

CFR1<25> = 0 (default). Shaped on-off keying is bypassed.

CFR1<25> = 1. Shaped on-off keying is enabled. See also CFR1<24>.

CFR1<24>:自动shaped On-off使能位 如果CFR<25>被清零,CFR<24>被忽略。

CFR<24>=0(默认)。手动Manual shaped on-off keying 操作,参看Shaped On-off Keying 部分详细资料。

CFR1<24>: Autoshaped On-Off Keying Enable Bit If CFR1<25> is cleared, CFR1<24> is ignored.

CFR1<24> = 0 (default). Manual shaped on-off keying operation. See the Shaped On-Off Keying section for details. CFR1<24> = 1. Autoshaped on-off keying operation. See the Shaped On-Off Keying section for details.

CFR1<23>:自动同步使能位

CFR<24>=0(默认)。多个的AD9954自动同步特征不被激活。 CFR<24>=1。多个的AD9954自动同步特征被激活。参看多个AD9954同步部分细节。

CFR1<23>: Automatic Synchronization Enable Bit

CFR1<23> = 0 (default). The automatic synchronization feature of multiple AD9954s is inactive.

CFR1<23> = 1. The automatic synchronization feature of multiple

AD9954s is active. See the Synchronizing Multiple AD9954s section for details.

CFR1<22>:多个AD9954软件手动同步

CFR1<22>=0(默认)。手动同步特征不被激活。

CFR1<22>=1。软件控制的手动同步特征被激活。SYNC_CLK上升沿被SYNC_CLK周期提前,并且这位被自动清零。为了提前上升沿若干倍,这个位需要被设置一次在在每个提前时。

CFR1<22>: Software Manual Synchronization of Multiple AD9954s CFR1<22> = 0 (default). The manual synchronization feature is inactive.

CFR1<22> = 1. The software-controlled manual synchronization feature is executed. The SYNC_CLK rising edge is advanced by one SYNC_CLK cycle, and this bit is autocleared. To advance the rising edge multiple times, this bit needs to be set once for each advance.

CFR1<21>:线性频率扫描使能

CFR1<21>=0(默认)。AD9954的线性频率扫描能力不被激活。 CFR1<21>=1。AD9954的线性频率扫描能力被激活。参看线性扫描部分详细内容。

CFR1<21>: Linear Frequency Sweep Enable

CFR1<21> = 0 (default). The linear frequency sweep capability of the AD9954 is inactive.

CFR1<21> = 1. The linear frequency sweep capability of the AD9954 is enabled. See the Linear Sweep Mode section for details.

CFR1<20:16>:不被使用,待清零 CFR1<20:16>: Not Used, Leave Clear

CFR1<15>:

CFR1<15>=0(默认)。直线扫描斜率被装载仅在超时上(时钟=1)时;它不被装载由于IO更新输入信号。

CFR1<15>=1。直线扫描斜率被装载在超时上(时钟=1)时,或者在IO更新输入信号的时。

CFR1<15>: Linear Sweep Ramp Rate Load Control Bit

CFR1<15> = 0 (default). The linear sweep ramp rate timer is loaded only upon timeout (timer == 1); it is not loaded due to an I/O update input signal.

CFR1<15> = 1. The linear sweep ramp rate timer is loaded either upon timeout (timer == 1) or at the time of an I/O update input signal

CFR1<14>:自动清除频率累加器位

CFR1<14>=0(默认)。当前频率累加器状态不被IO接受到的更新信号影响。

CFR1<14>=1。频率累加器被自动地或者同步地腾出一个周期接受一个IO口更新信号。

CFR1<14>: Autoclear Frequency Accumulator Bit

CFR1<14> = 0 (default). The current state of the frequency accumulator is not impacted by receipt of an I/O update signal. CFR1<14> = 1. The frequency accumulator is automatically and synchronously cleared for one cycle upon receipt of an I/O UPDATE signal

CFR1<13>:自动清零相位累加器位

CFR1<13>=0(默认)。当前相位累加器状态不被IO接受到的更新信号影响。

CFR1<13> = 1. 相位累加器被自动地或者同步地腾出一个周期接受一个IO口更新信号。

CFR1<13>: Autoclear Phase Accumulator Bit

CFR1<13> = 0 (default). The current state of the phase accumulator is not impacted by receipt of an I/O update signal. CFR1<13> = 1. The phase accumulator is automatically and synchronously cleared for one cycle upon receipt of an I/O

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