Metrology Requirements for the Semiconductor Industry

Metrology Requirements and the Limits of Measurement Technology for the Semiconductor Industry

Metrology Requirements and the Limits of Measurement Technology for the Semiconductor Industry Based on theAlain C. Diebold

Metrology Requirements and the Limits of Measurement Technology for the Semiconductor Industry

Measurements Today Atomic Dimensions Nanowire Transistor& Interconnectionsource source Gate drain Gate drainOpportunity for cross-work between industry and university

Metrology Requirements and the Limits of Measurement Technology for the Semiconductor Industry

AGENDA The ITRS Challenge Litho Metrology FEP Metrology Interconnect Metrology Materials Characterization

Metrology Requirements and the Limits of Measurement Technology for the Semiconductor Industry

ITRS Challenge2001 Leading Production Technology Node= DRAM½ Pitch MPU/ ASIC½ Pitch (nm) MPU Printed Gate Length (nm) MPU Physical Gate Length (nm) 130 nm 150 90 65 2002 115 nm 130 75 53

20032004 2007 2010 2013 2016

90nm 65 nm 45 nm 32 nm 22 nm 90 53 37 65 35 25 45 25 18 32 18 13 22 13 9

Leading Edge Tool Specifications set45 nm Node Metrology R&D Materials available 10 nm structures difficult to obtain

Beta Site 90 nm Node R&D 65 nm Node Early R&D 45 nm Node

Metrology Requirements and the Limits of Measurement Technology for the Semiconductor Industry

Process control Is based on Statistical SignificanceCP= CPK UL LLCP< 1MEASURED Cp/ACTUAL Cp100% 90% 80% 70% 60% 50% 40% 30% 0.75 1 1.25 1.5 1.75 2 2.25 2.5P/T=0.1 P/T=0.2 P/T=0.3 P/T=0.5 P/T=0.7 P/T=0.8 P/T=1.0

EFFECT OF P/T ON MEASURED Cp

6σ

CP= 1

ACTUAL Cp

CP> 1

If Distribution is Centered

Metrology Requirements and the Limits of Measurement Technology for the Semiconductor Industry

What are you Measuring?single value from distribution average

Distribution of linewidths inside test structure

test structure inside a die

Metrology Requirements and the Limits of Measurement Technology for the Semiconductor Industry

One Aspect of the Solution: Average over large area& Amplify Signal from Microscopic Changese.g. 150 nm lines 300 nm pitch

Optical CD using Overlay System

Rapid Sampling of test structures

S

L

Metrology Requirements and the Limits of Measurement Technology for the Semiconductor Industry

AGENDA How to control microscopic features Litho Metrology FEP Metrology Interconnect Metrology Materials Characterization

Metrology Requirements and the Limits of Measurement Technology for the Semiconductor Industry

Litho MetrologyCD Control Starts at the Mask6.35mm

22 nm Node - 2016Overlay and CD Control after Exposure

52 nm mask line width 26 nm scattering bars EUV CD Control after Etch 13 nm printed line width

9 nm physical line width

mm 152

m m 52 1

Metrology Requirements and the Limits of Measurement Technology for the Semiconductor Industry

Litho Metrology193 nmTechnology Node Lithography Metrology

157 nm EUV

130 nm 90nm 65 nm 45 nm 32 nm 22 nm Driver5.3 1.1 4.5 0.9 3 0.6 2.7 0.54 2 0.4 1.8 0.36 1.5 0.3 1.3 0.26 1.1 0.2 0.9 0.18 0.7 0.1 0.65 0.13

Printed Gate CD Control (nm) Wafer CD 3σ Precision P/T=0.2 Line Edge Roughness (nm) Precision for LER

MPU MPU MPU

193 and 157 nm EUV

Metrology Requirements and the Limits of Measurement Technology for the Semiconductor Industry

Low Energy SEM for CD MeasurementsTop Down Image

FE source Secondary Electron Detector Scanning coils

wafer

Lens

Sample Stage

Thanks to David Joy

Metrology Requirements and the Limits of Measurement Technology for the Semiconductor Industry

Limits of SEM for CD MeasurementsTBW=ζ

Loss of Depth of FieldCD 20 nm

DoF= (resolution)/(convergence angle)

10 nm TBW=ζ CD 5 nm Gabor’s limit

Thanks to David Joy

Metrology Requirements and the Limits of Measurement Technology for the Semiconductor Industry

Challenges: Round Top Resist& LERLine Edge Roughness Requires Better Dimensional Precision

50 nm

?50 nm

Metrology Requirements and the Limits of Measurement Technology for the Semiconductor Industry

Lithography CD MetrologyImprove CD-SEM thru 65 nm node High Voltage CD-SEM

100– 200 keV e-

Comparison of conventional SE (left) and Low Loss (right) images of copper interconnects. Note the greatly enhanced surface detail and lack of edg

e brightness in the Low Loss image.Low loss detectorMicrograph courtesy of O C Wells

Figures from David Joy

Metrology Requirements and the Limits of Measurement Technology for the Semiconductor Industry

3D CD Metrology

SEM– Scatterometry– CD-AFM

Commercially availableSoftware comparison of top down line scan of edge to golden image Tilt Beam SEM600

R&D

Software to convert top down image to 3D image

5500 400

300

200

Scatterometry0 -480 -400 -320 -240 -160 -80 0 80 160

100

CD-AFM Dual Beam FIB (destructive)

Metrology Requirements and the Limits of Measurement Technology for the Semiconductor Industry

Scatterometry for CD MeasurementsMirror

Θ in=Θ outMulti-wavelength Light Source Polarization Sensitive Detector

Real Time Calculation of line width& shape Eliminates Libraries600

5500 400

Incident Polarized White Light

300

200

0th order

100

0 -480

-400

-320

-240

-160

-80

0

80

160