MSTM-S3-TR-SS-077.76M中文资料

MSTM-S3-TRStratum 3

Timing Module

BulletinTM027Page1 of 16RevisionP05

Date02 DEC 02

Issued By

Application

Features

The Connor-Winfield MSTM-S3-TR

5V Miniature TimingSimplified Control Timing Module acts as aModulecomplete system clock module for Stratum 3 Redundanttiming applications in accordance with GR-References1244, Issue 2 and GR-253, Issue 3.

2 SynchronousConnor Winfield’s Stratum 3 timing modulesOutputs Availablehelps reduce the cost of your design byFrom 8 kHz to77.76MHzminimizing your development time and

40 sec., Filtered,maximizing your control of the system clockHold Over Historywith our simplified design.

Operational Status

Flags

General Description

The Connor-Winfield Stratum 3 Simplified Control Timing Mod-ule acts as a complete system clock module for general Stratum3 timing applications. The MSTM is designed to replace similarunits from TF Systems (TF118B) and Raltron (SY0001B).

Full external control input allows for selection and monitoringof any of four possible operating states: 1) Holdover, 2) ExternalReference #1, 3) External Reference #2, and 4) Free Run. Table#1 illustrates the control signal inputs and corresponding opera-tional states.

In the absence of External Control Inputs (A,B), the MSTMenters the Free Run mode and signals an External Alarm. TheMSTM will enter other operating modes upon application of aproper control signal. Mode 1 operation (A=1, B=0) results in anoutput signal that is phase locked to the External ReferenceInput #1. Mode 2 operation (A=0, B=1) results in an output sig-nal that is phase locked to External Reference Input #2. Hold-over mode operation (A=1, B=1) results in an output signal at ornear the frequency as determined by the latest (last) locked-signal input values and the holdover performance of the MSTM.Free Run ModeFree Run mode operation (A=0, B=0) is a guar-anteed output of 4.6 ppm of the nominal frequency.

Alarm signals are generated at the Alarm Output during Hold-over and Free Run operation. Alarm Signals are also generatedby Loss-of-Lock and Loss-of-Reference conditions. A high levelindicates an alarm condition. Real-time indication of the opera-tional mode is available at unique operating mode outputs onpins 1-4.

Control loop 0.1 Hz filters effectively attenuate any referencejitter, smooth out phase transients, comply with wander transferand jitter tolerances.

Functional Block Diagram

Figure 1

Function Control Table

Table 1

AB01

00

Operational

Mode

Free Run (Default Mode) Hold Over

Ref 101000

Ref 200100

Hold Over

00011

10000

00000

Alarm Out

10011

01

11

Absolute Maximum Rating

Table 2

SymbolVCCVITs

Parameter

Power Supply VoltageInput VoltageStorage Temperature

Minimum-0.5-0.5-55

Nominal

Maximum7.0VCC + 0.5100

UnitsVoltsVoltsdeg. C

Notes1.01.01.0

Recommended Operating Conditions

Table 3

SymbolVccVTHVIHVILtINCINVOHVOLtTRANS

Parameter

Power supply voltageReset threshold voltageHigh level input voltage - TTLLow level input voltage - TTLInput signal transition - TTLInput capacitanceHigh level output voltage, IOH = -4.0mA, VCC = min.Low level output voltage, IOL = 12.0 mA, VCC = min.Clock output transition time

2.4Minimum4.754.252.00

Nominal5.00

Maximum5.254.5VCC0.8250155.250.4

UnitsVoltsVoltsVoltsVoltsnspFVoltsVolts

2.0Notes

4.0

300

70

nsns°C

tPULSETOP

8kHz input reference pulsewidth( positive or negative)Operating temperature

Specifications

Table 4

Parameter

Frequency Range (Sync_Out)Frequency Range (Opt_Out)Supply Current

Timing Reference Inputs

Jitter, Wander and Phase Transient TolerancesWander GenerationWander TransferJitter GenerationJitter TransferPhase TransientsFree Run AccuracyHold Over Stability

Inital OffsetTemperatureDrift

Maximum Hold Over HistoryPull-in/ Hold-in RangeLock TimeDPLL Bandwidth

Specifications8 kHz to 77.76 MHz8 kHz to 77.76 MHz

250 mA typical, 400 mA during warm-up (Maximum)8 kHz - 19.44 MHz

GR-1244-CORE 4.2-4.4, GR-253-CORE 5.4.4.3.6GR-1244-CORE 5.3, GR-253-CORE 5.4.4.3.2GR-1244-CORE 5.4

GR-1244-CORE 5.5, GR-253-CORE 5.6.2.3GR-1244-CORE 5.5, GR-253-CORE 5.6.2.1GR-1244-CORE 5.6, GR-253-CORE 5.4.4.3.34.6 ppm over TOP

±0.37 ppm for initial 24 hrs ±0.05 ppm ±0.28 ppm ±0.04 ppm40 seconds

±13.8 ppm minimum30 seconds typical< 0.1 Hz

5.04.0

3.0Notes

NOTES:

1.0:Stresses beyond those listed under Absolute Maximum Rating may cause damage

to the device. Operation beyond Recommended Conditions is not implied.2.0:

Logic is 3.3V CMOS3.0 GR-1244-CORE 3.2.1

4.0:5.0:

Hold Over stability is the cumulative fractional frequency offset as described byGR-1244-CORE, 5.2

Pull-in Range is the maximum frequency deviation from nominal clock rate on the

reference inputs to the timing module that can be overcome to pull into synchronizationwith the reference

Pin Description

Table 5Pin #

1 2 3 4 5 6 7 8 9101112131415161718

Connection

Hold OverRef 1Ref 2Free RunGNDAlarm _OutCNTL ACNTL BPLL_UnlockTri-State/GNDSync_OutGNDOpt_OutGNDEx_Ref_2GNDEx_Ref_1Vcc

Description

Indicator output. High output when Hold Over mode is selected by control pins.Indicator output. High output when Ref 1 mode is selected by control pins.Indicator output. High output when Ref 2 mode is selected by control pins.Indicator output. High output when Free Run mode is selected by control pins.Ground

Alarm output. High output if module is in Free Run, or Hold Over, o …… 此处隐藏：7476字，全部文档内容请下载后查看。喜欢就下载吧 ……