基于FPGA的多路彩灯控制器的设计(2)

5.2.1 时序控制器：SXKZ部分

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all; --库函数声明 entity sxkz is --实体声明 port(

chose_key:in std_logic; --速度控制按钮 clk_in:in std_logic; --输入时钟信号 clr:in std_logic; --复位信号

clk:out std_logic --改变后的时钟信号 );

end entity;

architecture art of sxkz is --结构体声明 signal cllk:std_logic; begin

process(clk_in,clr,chose_key)is --进程

variable temp:std_logic_vector(0 to 2); --定义一个变量 begin

if clr='1' then cllk<='0';temp:=\复位初始化 elsif rising_edge (clk_in) then

if chose_key='1' then --按键按下，高速时

if temp=\输出时钟信号T为输入信号的8倍 temp:=\

cllk<=not cllk; else temp:=temp+'1'; end if; else

if temp=\按键没按下，低速时 temp:=\输出时钟信号T为输入信号的 cllk<=not cllk; --16倍 else temp:=temp+'1'; end if; end if; end if;

end process; clk<=cllk; end art;

生成的元器件符号SYMBOL:

- - 6 - -

图5.2 时序控制器

5.2.2，显示控制器：XSKZ

library ieee;

use ieee.std_logic_1164.all; entity xskz is port(

clk:in std_logic; clr:in std_logic;

led:out std_logic_vector(0 to 15) --彩灯输出，控制端口 );

end entity;

architecture art of xskz is

type state is(s0,s1,s2,s3,s4,s5,s6); --定义一组状态机 signal current_state:state;

signal flower:std_logic_vector(15 downto 0); --定义一信号 begin

process(clr,clk) is

constant f1:std_logic_vector(0 to 15):=\ constant f2:std_logic_vector(0 to 15):=\ constant f3:std_logic_vector(0 to 15):=\ constant f4:std_logic_vector(0 to 15):=\ constant f5:std_logic_vector(0 to 15):=\ constant f6:std_logic_vector(0 to 15):=\--定义一组彩灯的花式。 begin

if clr='1' then current_state<=s0; --判断复位信号，有则复 elsif rising_edge(clk) then --位状态为0，否则等待 case current_state is --时钟信号的上升沿 when s0=>

flower<=\初始状态 current_state<=s1; --一个时钟上升沿，将当前状态指向下一个状态 when s1=> flower<=f1;

- - 7 - -

current_state<=s2; when s2=> flower<=f2;

current_state<=s3; when s3=> flower<=f3;

current_state<=s4; when s4=> flower<=f4;

current_state<=s5; when s5=> flower<=f5;

current_state<=s6; when s6=> flower<=f6;

current_state<=s1; -- end case; end if; end process;

led<=flower; end architecture;

flower<=f3;

current_state<=s4; when s4=> flower<=f4;

current_state<=s5; when s5=> flower<=f5;

current_state<=s6; when s6=> flower<=f6;

current_state<=s1; -- end case; end if; end process;

led<=flower; end architecture;

生成元器件符号：SYMBOL

- - 8 - -

返回第一个状态，实现循环返回第一个状态，实现循环

图5.3 显示控制器

5.2.3 彩灯控制器：CDKZ

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity cdkz2 is --实体 port( clkin:in std_logic; --端口定义 clr:in std_logic; chose_key:in std_logic; led:out std_logic_vector(0 to 15) );

end entity;

architecture art of cdkz2 is --结构体

component sxkz is --元件例化sxkz port( chose_key:in std_logic; clk_in:in std_logic; clr:in std_logic; clk:out std_logic );

end component sxkz;

component xskz is --元件例化xskz port( clk:in std_logic; clr:in std_logic; led:out std_logic_vector(0 to 15) );

end component xskz;

signal s0:std_logic; --定义一个信号 begin

- - 9 - -

u1:sxkz port map(chose_key,clkin,clr,s0); u2:xskz port map(s0,clr,led); end architecture;

彩灯控制器SYMBOL：

图5.4 彩灯控制器

图5.5 RTL

六、仿真调试分析

start compilation先编译

generate functional simulation netlist然后生成功能仿真网络表 assignments–setting—simulation setting设置成功能仿真 然后新建一个vector waveform file

通过view—utility windows--node finder 把输入输出管脚添加进波形仿真图里 点击start simulation

6.1 时序控制器波形仿真：

- - 10 - -