并行CRC8 Verilog实现

/*****************************************************************************/ // CRC8 Calculate

// CRC8 Generator Polynomial : x ^ 8 + x ^ 2 + x ^ 1 + 1

/******************************************************************************/

module CRC8_D8;

// polynomial: (0 1 2 8) //

// data width: 8

// convention: the first serial bit is D[7] function [7:0] nextCRC8_D8;

input [7:0] Data; input [7:0] crc; reg [7:0] d; reg [7:0] c;

reg [7:0] newcrc; begin d = Data; c = crc;

newcrc[0] = d[7] ^ d[6] ^ d[0] ^ c[0] ^ c[6] ^ c[7]; newcrc[1] = d[6] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[6];

newcrc[2] = d[6] ^ d[2] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[2] ^ c[6]; newcrc[3] = d[7] ^ d[3] ^ d[2] ^ d[1] ^ c[1] ^ c[2] ^ c[3] ^ c[7]; newcrc[4] = d[4] ^ d[3] ^ d[2] ^ c[2] ^ c[3] ^ c[4]; newcrc[5] = d[5] ^ d[4] ^ d[3] ^ c[3] ^ c[4] ^ c[5]; newcrc[6] = d[6] ^ d[5] ^ d[4] ^ c[4] ^ c[5] ^ c[6]; newcrc[7] = d[7] ^ d[6] ^ d[5] ^ c[5] ^ c[6] ^ c[7]; nextCRC8_D8 = newcrc; end

endfunction endmodule