中南大学计算机体系结构模拟试题试卷(2)

– Use the revised MIPS pipeline where there is forwarding and where branches are handled in the ID stage

? Assume 50% of all loads cause RAW hazards because the loaded datum is used by the following ALU

instruction

? Assume 60% of all branches have RAW hazards with the immediately preceding ALU operation (e.g., a

compare) ? Assume branches are handled by flushing the instruction in the IF stage as soon as the branch is decoded

in the ID stage ?

八．A CISC machine has a CPI of 4 for load/store, 3 for ALU/branch, 10 for call/return, and a CPU clock rate of 1.75 GHz. A RISC machine has a CPI of 1.2 (as it is pipelined) and a CPU clock rate of 1 GHz. Because the CISC machine can use complex instructions, the typical program is shorter. In this case, assume we have a benchmark that has 38% loads, 10% stores, 35% ALU operations, 3% calls, 3% returns, and 11% branches. If the CISC program is 40% shorter, which machine will run the benchmark in less time?

For each of the following compiler optimizations below, briefly explain whether the optimization will provide a CPU performance increase because it will reduce CPI, reduce IC, reduce both, or reduce neither (in which case, how does the optimization provide a benefit for the execution time of the program?) See figure 2.25 on page 124 and the descriptions of these in the text on pages 121-123.

a. Code motion

b. Register optimization with graph coloring c. Procedure integration d. Pipeline scheduling

e. Global common subexpression elimination f. Copy propagation

九、 Given the following MIPS floating point code, and the floating point pipeline where forwarding is available and branches are handled in the ID stage by flushing the current instruction, but where two or more instructions that reach the MEM stage at the same clock cycle will require that latter instruction(s) be stalled,

Loop: L.S F1, 40(R3) MUL.S F3, F1, F2 // assume F2 is already loaded L.S F5, 0(R6)

SUB.S F4, F3, F5 S.S F4, 0(R6)

DADDI R3, R3, #4 DADDI R6, R6, #4

DSUBI R10, R10, #1 BNEZ R10, Loop

a. provide a timing diagram of 1 iteration of the loop plus the first instruction of the second iteration.

b. schedule the code to remove as many stalls as possible assuming a branch delay slot is available, and show the timing

diagram for 1 iteration plus the first instruction of the next for your scheduled code.

c. assuming that the loop iterates 1000 times, how much faster is the code in part b over part a?

十.假设在一个采用组相联映象的Cache存储器中，Cache的容量为1KB，要求Cache的每一块在一个主存周期内能从主存取得。主存采用模32交叉，每个分体的宽度为64位，主存的总容量为4MB。采用按地址访问存储器构成的相联目录表，实现主存地址到Cache地址的变换，并约定采用2个外相等比较电路。

(1)请设计主存地址格式和Cache地址格式，并标出各段的位数；

(2)若替换算法采用LRU算法，对于如下主存块地址流：1、4、1、4、7、1、9、4、27、7，如主存中内容一开始未装入Cache中，请列出随时间变化Cache中各块的使用状况，求出此期间Cache的块命中率。

十一.假设在一台40MHz处理机上运行200000条指令的目标代码，程序主要由四种类型的指令所组成。根据程序跟踪实验结果，已知指令混合比和每类指令的CPI值如下表所示。

指令类型 算术和逻辑 高速缓存命中的加载/存储 转移 高速缓存缺失的存储器访问 指令混合比 60% 18% 12% 10% CPI 1 2 4 8 (1)试计算用上述跟踪数据在单处理机上执行该程序时的平均CPI； (2)根据(1)所得到的CPI，计算相应的MIPS速率及程序的执行时间。

十二. 有8台外设，各设备要求传送信息的工作速率如图所示。现设计的通道，在数据传送期，每选择一次设备需2us，每传送一个字节数据也需要2us。

1、若用作字节多路通道，通道的最高流量是多少？

2、作字节多路通道时，希望同时不少于4台设备挂在此通道上，最好多挂一些，且高速设备尽量多挂一些，请问应选哪些设备挂在此通道上？为什么？

3、若用作数组多路通道，通道工作和最高流量是多少？（设定长块大小取成512B） 4、作数组多路通道用时，应选哪些设备挂在通道上，为什么？

设备标识 工作速率（KB/S） A B C D E F G H 500 240 100 75 50 40 14 10 十三、报文由A～K字符组成，其出现频度依次为0.17, 0.05, 0.20, 0.06, 0.08, 0.03, 0.01, 0.08, 0.13, 0.08, 0.11。

（1） 各字符用等长二进制编码，传送200个字符时，需传送多少个二进制码位？ （2） 构造哈夫曼树，写出各字符的二进制码位数。 （3） 按哈夫曼编码，计算字符的平均码长。

（4） 用哈夫曼码传送1000个字符，比定长码传送可减少传送的码位数是多少？ 设计一种平均码长最短的仅有两种码长的扩展操作码编码，并求出其平均码长。