数字电路与逻辑设计实验(3)

yibu：

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY yibu IS PORT(

cp,clear:IN STD_LOGIC;

q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ); END yibu;

ARCHITECTURE a OF yibu IS

SIGNAL temp:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN PROCESS(cp) BEGIN IF clear='1' THEN temp<=\

elsIF temp=\ temp<=\ else

IF (cp'event and cp='1') THEN temp<=temp+1; END IF; end if;

END PROCESS; q<=temp; END a;

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY seg7_1 IS PORT(

a:IN STD_LOGIC_VECTOR (3 downto 0); b:OUT STD_LOGIC_VECTOR(6 downto 0); c,d,e,f,g,h:OUT STD_LOGIC );

数码管译码器VHDL代码： end seg7_1;

ARCHITECTURE seg7_1_arch OF seg7_1 IS BEGIN

c<='0';d<='1';e<='1';f<='1';g<='1';h<='1'; PROCESS (a) BEGIN CASE a IS

WHEN\ --0 WHEN\ --1 WHEN\ --2 WHEN\ --3 WHEN\ --4 WHEN\ --5 WHEN\ --6 WHEN\ --7 WHEN\ --8 WHEN\ --9

WHEN OTHERS =>B<=\ END CASE; END PROCESS; END;

（3） 实验四

（1） 数据管串行扫描电路：

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY chuanxing IS PORT(

clk,clear:IN STD_LOGIC;

guan:out STD_LOGIC_VECTOR (6 downto 0); xuan:OUT STD_LOGIC_VECTOR(5 downto 0) );

end chuanxing;

ARCHITECTURE yu OF chuanxing IS signal status:integer range 0 to 6; BEGIN process(clk) begin

if clear='0' then status<=0; elsif (clk'event and clk='1')then if status=6 then status<=1; else

status<=status+1; end if;

end if; end process;

PROCESS (status) BEGIN

CASE status IS

WHEN 1=>guan<=\ WHEN 2=>guan<=\ WHEN 3=>guan<=\ WHEN 4=>guan<=\ WHEN 5=>guan<=\ WHEN 6=>guan<=\ WHEN OTHERS=>guan<=\ END CASE; END PROCESS; END;

（2） 循环左滚动：

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY move IS

PORT( clk,clear:IN STD_LOGIC;

guan:OUT STD_LOGIC_VECTOR(6 DOWNTO 0); xuan:OUT STD_LOGIC_VECTOR(5 DOWNTO 0)); END move;

ARCHITECTURE zuo OF move is

SIGNAL l:STD_LOGIC_VECTOR(6 DOWNTO 0);

SIGNAL c:STD_LOGIC_VECTOR(5 DOWNTO 0); SIGNAL cnt,cnt1:INTEGER RANGE 0 TO 5; SIGNAL tmp:INTEGER RANGE 0 TO 1999; signal clk1:STD_LOGIC; BEGIN

Fenpin1:PROCESS(clk,clear) BEGIN

IF clear='0' THEN tmp<=0;

ELSIF clk'EVENT AND clk='1' THEN IF tmp=1999 THEN

tmp<=0;

ELSE tmp<=tmp+1; END IF; END IF;

END PROCESS fenpin1; fenpin2:PROCESS(tmp) BEGIN

IF clk'EVENT AND clk='1' THEN IF tmp<1000 THEN clk1<='0'; ELSE clk1<='1'; END IF; END IF;

END PROCESS fenpin2; change:PROCESS(clk)