W5500中文数据手册 - V1.1(6)

2.4.1

写访问——FDM模式

1字节写访问

表14表FDM表表表，1表表表表表SPI表表表

2字节写访问

表15表FDM表表表，2表表表表表SPI表表表

4字节写访问

表16表FDM表表表，4表表表表表SPI表表表

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2.4.2 读访问——FDM模式

1字节读访问

表17表FDM表表表，1表表表表表SPI表表表

2字节读访问

表18表FDM表表表，2表表表表表SPI表表表

4字节读访问

表19表FDM表表表，4表表表表表SPI表表表

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3 寄存器和内存构成

W5500有1个通用寄存器，8个Socket寄存器区，以及对应每个Socket的收/发缓存区。每个区域均通过SPI数据帧的区域选择位（BSB[4:0]）来选取。图20显示了区域选择位（BSB[4:0]）选择的区域以及收/发缓存区的可用偏移地址范围。每一个Socket的发送缓存区都在一个16KB的物理发送内存中，初始化分配为2KB。每一个Socket的接收缓存区都在一个16KB的物理接收内存中，初始化分配为2KB。

无论给每个Socket分配多大的收/发缓存，都必须在16位的偏移地址范围内（从0x0000 到 0xFFFF）。

关于16KB收/发内存的构成及访问方式的更多信息，请参考‘3.3章节’。

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16bist Offset AddressValid Range0xFFFFBlock Select BitsBlocksPhysical 16KB RX Memory0x3FFF0x3E2C0x380011111 (0x1F)Socket 7 RX Buffer11110 (0x1E)Socket 7 TX Buffer11101 (0x1E)Socket 7 Register11100 (0x1C)Reserved11011 (0x1B)Socket 6 RX Buffer11010 (0x1A)Socket 6 TX Buffer11001 (0x19)Socket 6 Register11000 (0x18)Reserved10111 (0x17)Socket 5 RX Buffer10110 (0x16)Socket 5 TX Buffer10101 (0x15)Socket 5 Register10100 (0x14)Reserved...0xF8000xF7FFSocket 7 RX Buffer (2KB)Socket 6RX Buffer (2KB)Socket 5RX Buffer (2KB)Socket 4RX Buffer (2KB)Socket 3RX Buffer (2KB)Socket 2RX Buffer (2KB)Socket 1RX Buffer (2KB)Socket 0RX Buffer (2KB)0xF0000xEFFF0x3000...0x2800Socket 7 RX Buffer...0x9E2C0x20000x10000x0FFF0x18000x08000x07FF0x10000x0FFF0x08000x00000x0000...10011 (0x13)Socket 4 RX Buffer10010 (0x12)Socket 4 TX Buffer10001 (0x11)Socket 4 Register01000 (0x10)Reserved01111 (0x0F)Socket 3 RX Buffer01110 (0x0E)Socket 3 TX Buffer01101 (0x0D)Socket 3 Register01100 (0x0C)Reserved01011 (0x0B)Socket 2 RX Buffer01010 (0x0A)Socket 2 TX Buffer01001 (0x09)Socket 2 Register01000 (0x08)Reserved00111 (0x07)Socket 1 RX Buffer00110 (0x06)Socket 1 TX Buffer00101 (0x05)Socket 1 Register00100 (0x04)Reserved00011 (0x03)Socket 0 RX Buffer00010 (0x02)Socket 0 TX Buffer00001 (0x01)Socket 0 Register00000 (0x00)Common RegisterPhysical 16KB TX Memory0x3FFF0xFFFF0x38000xF8000xF7FF0x30000xF0000xEFFFSocket 7TX Buffer (2KB)Socket 6TX Buffer (2KB)Socket 5TX Buffer (2KB)Socket 4TX Buffer (2KB)Socket 3TX Buffer (2KB)Socket 2TX Buffer (2KB)Socket 1TX Buffer (2KB)Socket 0TX Bufer (2KB)Socket 1 TX Buffer...ReservedSocket 0 RegisterReservedCommon Register表20表表表表表表表表

...0x2800...0x413C0x20000x18000x10000x0FFF0x10000x0FFF0x093C0x08000x08000x07FF0x00000x0000...0xFFFF0x00310x00300x00000xFFFF0x003A0x00390x0000

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3.1 通用寄存器区

通用寄存器区配置了W5500的基本信息，例如：IP及MAC地址。该区域可以通过SPI数据帧的区域选择位(BSB[4:0])选定（见表3）。表4 描述了通用寄存器的偏移地址。对于每个寄存器的详细信息，请参考‘4.1章节’。

表表4表表表表表表表表表表

Offset 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F 0x0010 0x0011 0x0012

Mode (MR)

Register

Offset Register

Interrupt Low Level Timer (INTLEVEL0) (INTLEVEL1) Interrupt (IR)

Interrupt Mask (IMR)

Socket Interrupt (SIR)

Socket Interrupt Mask (SIMR) Retry Time (RTR0) (RTR1) Retry Count (RCR)

PPP LCP RequestTimer (PTIMER)

PPP LCP Magic number (PMAGIC)

PPP Destination MAC Address (PHAR0) (PHAR1) (PHAR2)

Offset 0x0021 0x0022 0x0023 0x0024 0x0025 0x0026 0x0027 0x0028 0x0029 0x002A 0x002B 0x002C 0x002D 0x002E 0x002F ~ 0x0038 0x0039

(PHAR3) (PHAR4) (PHAR5)

Register

0x0013 0x0014 0x0015 0x0016 0x0017 0x0018 0x0019 0x001A 0x001B 0x001C 0x001D 0x001E 0x001F 0x0020 Reserved

Gateway Address (GAR0) (GAR1) (GAR2) (GAR3)

Subnet Mask Address (SUBR0) (SUBR1) (SUBR2) (SUBR3)

Source Hardware Address (SHAR0) (SHAR1) (SHAR2) (SHAR3) (SHAR4) (SHAR5)

Source IP Address (SIPR0) (SIPR1) (SIPR2) (SIPR3)

PPP Session Identification (PSID0) (PSID1)

PPP Maximum Segment Size (PMRU0) (PMRU1)

Unreachable IP address (UIPR0) (UIPR1) (UIPR2) (UIPR3)

Unreachable Port (UPORTR0) (UPORTR1) PHY Configuration (PHYCFGR)

Reserved

Chip version (VERSIONR)

0x003A ~ 0xFFFF

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