电子设计自动化(EDA)_数字时钟程序模块(LED数码管显示)_实验报告

6个数码管动态扫描显示驱动 带闹钟功能 EDA程序 24、60计数器 复用 扫描模块

电子设计自动化(EDA)—数字时钟LED数码管显示

二、实验内容和实验目的

1．6个数码管动态扫描显示驱动

2．按键模式选择(时\分\秒)与闹钟(时\分)调整控制,

3．用硬件描述语言(或混合原理图)设计时、分、秒计数器模块、闹钟模块、按键控制状态机模块、动态扫描显示驱动模块、顶层模块。要求使用实验箱左下角的6个动态数码管(DS6 A~DS1A)显示时、分、秒；要求模式按键和调整按键信号都取自经过防抖处理后的按键跳线插孔。

实验目的： 1）学会看硬件原理图，2）掌握FPGA硬件开发的基本技能

3）培养EDA综合分析、综合设计的能力 三、实验步骤、实现方法(或设计思想)及实验结果

主要设备: 1）PC机，2）硬件实验箱，3）Quartus II软件开发平台。 1．打开Quartus II ，连接实验箱上的相关硬件资源，如下图1所示。 2．建立新文件，选择文本类型或原理图类型。 3．编写程序。 4．编译

5．仿真，加载程序到芯片，观察硬件输出结果(数码管显示)

6．结果正确则完成。若结果不正确，则修改程序，再编译，直到正确。 模24计数器模块 LIBRARY IEEE; IF(en='1') THEN USE IEEE.STD_LOGIC_1164.ALL; IF(a="0010" AND b="0011") THEN USE IEEE.STD_LOGIC_UNSIGNED.ALL; a<="0000"; USE IEEE.STD_LOGIC_ARITH.ALL; b<="0000"; ENTITY count24 IS ELSE IF(b="1001") THEN PORT(clk,en:IN STD_LOGIC; a<=a+'1'; cout:OUT STD_LOGIC; b<="0000"; hh,hl:OUT STD_LOGIC_VECTOR(3 ELSE b<=b+'1'; DOWNTO 0)); END IF; END count24; END IF; ARCHITECTURE arc OF count24 IS IF(a="0010" AND b="0010") THEN SIGNAL a,b:STD_LOGIC_VECTOR(3 DOWNTO cout<='1'; 0); ELSE cout<='0'; BEGIN END IF; PROCESS(clk,en) END IF; BEGIN END IF; hh<=a; END PROCESS; hl<=b; END arc; IF(clk'EVENT AND clk='1') THEN

6个数码管动态扫描显示驱动 带闹钟功能 EDA程序 24、60计数器 复用 扫描模块

模60计数器模块 LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY count60 IS

PORT(clk,en:IN STD_LOGIC; cout:OUT STD_LOGIC; hh,hl:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END count60;

ARCHITECTURE arc OF count60 IS

SIGNAL a,b:STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL sout:STD_LOGIC; BEGIN

PROCESS(clk) BEGIN hh<=a;

4-7显示译码模块 LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY segment4to7 IS

PORT(s:IN STD_LOGIC_VECTOR(3 DOWNTO 0); a,b,c,d,e,f,g:OUT STD_LOGIC); END segment4to7;

ARCHITECTURE arc OF segment4to7 IS

SIGNAL y:STD_LOGIC_VECTOR(6 DOWNTO 0); BEGIN a<= y(6); b<= y(5); c<= y(4); d<= y(3); e<= y(2);

hl<=b;

IF(clk'EVENT AND clk='1') THEN IF(en='1') THEN IF(a="0101" AND b="1001") THEN a<="0000"; b<="0000"; ELSE IF(b="1001") THEN a<=a+'1'; b<="0000"; ELSE b<=b+'1'; END IF; END IF; END IF; END IF;

END PROCESS;

sout<='1' WHEN a="0101" AND b="1001" ELSE '0';

cout<=sout AND en; END arc;

f<= y(1); g<= y(0); PROCESS(s) BEGIN CASE s IS

WHEN "0000"=>y<="1111110"; WHEN "0001"=>y<="0110000"; WHEN "0010"=>y<="1101101"; WHEN "0011"=>y<="1111001"; WHEN "0100"=>y<="0110011"; WHEN "0101"=>y<="1011011"; WHEN "0110"=>y<="1011111"; WHEN "0111"=>y<="1110000"; WHEN "1000"=>y<="1111111"; WHEN "1001"=>y<="1111011"; WHEN OTHERS=>y<="0000000"; END CASE; END PROCESS; END arc;

6个数码管动态扫描显示驱动 带闹钟功能 EDA程序 24、60计数器 复用 扫描模块

带闹钟控制模块 LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY mode_adjust_with_alarm IS

PORT (adjust,mode,clk1hz: IN STD_LOGIC;

clkh,enh,clkm,enm,clks,enha: OUT STD_LOGIC; clkh_a,clkm_a:OUT STD_LOGIC; mode_ss: OUT STD_LOGIC_VECTOR(2 DOWNTO 0)); END mode_adjust_with_alarm;

ARCHITECTURE arc OF mode_adjust_with_alarm IS TYPE mystate IS (s0,s1,s2,s3,s4,s5); SIGNAL c_state,next_state: mystate; BEGIN

PROCESS (c_state) BEGIN CASE c_state IS

WHEN s0=> next_state <= s1; clkh<=clk1hz; clkm<=clk1hz; clks<=clk1hz;

enh<='0'; enm<='0'; enha<='0'; clkh_a<= '0'; clkm_a<= '0'; mode_ss <="000";

WHEN s1=> next_state <= s2; clkh<=adjust; clkm<= '0'; clks<='0';

enh<='1'; enm<='0';enha<='0'; clkh_a<= '0';clkm_a<= '0'; mode_ss <="001";

WHEN s2=> next_state <= s3; clkh<= '0'; clkm<=adjust; clks <= '0';

enh<='0';enm<='1';enha<='0'; clkh_a<= '0'; clkm_a<= '0'; mode_ss <="010";

WHEN s3=> next_state <= s4; clkh<= '0'; clkm<= '0'; clks<=adjust;

enh<='0'; enm<='0';enha<='0'; clkh_a<= '0'; clkm_a<= '0'; mode_ss <="011";

WHEN s4=> next_state <= s5; clkh<= clk1hz; clkm<= clk1hz; clks<=clk1hz;

enh<='0';enm<='0';enha<='1'; clkh_a<=adjust; clkm_a<= '0'; mode_ss <="100";

WHEN s5=> next_state <= s0; clkh<= clk1hz; clkm<= clk1hz; clks<=clk1hz;

enh<='0'; enm<='0'; enha<='0'; clkh_a<= '0'; clkm_a<=adjust; mode_ss <="101";

END CASE; END PROCESS;

PROCESS (mode) BEGIN

IF (mode'EVENT AND mode='1') THEN c_state<=next_state ; END IF; END PROCESS; END arc;

6个数码管动态扫描显示驱动 带闹钟功能 EDA程序 24、60计数器 复用 扫描模块

扫描模块

LIBRARY IEEE; WHEN s1=> next_state <=s2; ss<="011"; USE IEEE.STD_LOGIC_1164.ALL; WHEN s2=> next_state <=s3; ss<="100"; USE IEEE.STD_LO …… 此处隐藏：7449字，全部文档内容请下载后查看。喜欢就下载吧 ……