电子显微镜原理图

5

4

3

2

1

R1 1M XO Y1 12MHz VAA_2V8 VDDIO_2V8 R16 NC/0 R11 C4 11 10 47 46 41 38 42 45 44 48 43 40D

VDD18 XI C1 0.1uF RST

S_IMG8

VRES

DGND

S_IMG7

GPIO_0

GPIO_1

S_PCK

VDD18

R5

1.5K SDA SCL

S_PWR_DN

VDDIO_2V8

R4

1.5K S_HSYNC S_VSYNC

C2 22pF

C3 22pF RST XO

DGND

DGND

R3 56K

VDDD

DGND U2 SGND 12 13 14 39 6 37 8 9 7 5

NC/0 0.1uF SGND VAA_2V8 C5

ASIC reset

D

STROBE

SDATA

SCLK

P_CLK

XOUT

TEST

RST

GPIO_0

GPIO_1

GPIO_2

VDD33

VSS

VDD18

S_IMG_8

VDDIO AGND

M_CLOCK DOUT0

4 3 2 1 28 27 26

SEN_CLK VDD_1V8 S_IMG0 C6 0.1uF S_IMG1 S_IMG2 DGND

R6 2.4K VDDU DGND DGND

XI

1 2 3

XIN VDDL VSSL

SD_PWR_DN

S_IMG_7

AGND

F_VALID

L_VALID

VDD33 GPIO_3 S_IMG_6

36 35 34 33 32 31 30 29 28 27 26 25

VDDD

VAA DOUT1 SCAN RESET STANDBY DOUT2 SADDR DOUT9 DOUT8 DOUT7 DOUT6 DOUT5 DOUT4 DOUT3 OE# VDD DGND

15 10uF 16 DGND SGND VDDIO_2V8 R7 NC/10K R8 GPIO_0 0 C8 NC/1uF 17 18

S_IMG6 S_IMG5 S_IMG4 VDDD 2 VDD18 S_IMG3 S_IMG2 S_IMG1 S_IMG0 R9 1.5K GPIO_1 DGND SW2 SW-KEY 1 VDD_3V3

K82&K12&MI1310

VRESBe closed to ASIC"pin7-VRES"VDDU

DM DP

4 5 6

DM S_IMG_5 DP VDDPH VRES VSSPH VDDR S_IMG_3 VDDLRFG S_IMG_2 VSDLC S_IMG_1 S_HSYNC S_VSYNC SEN_CLK SF_CS_ SF_SCK S_PCK SF_SO VDD18 VDD33 SF_SI SDA VSS SCL S_IMG_0 S_IMG_4 VDD33 VSS VDD18

VRES DGND VDDU C7 VDD18

7 8 9 10 11

U1 SN9C288P - LQFP48

19

20

21

22

23

24 S_IMG4

S_IMG8

S_IMG7

S_IMG6

S_IMG5

S_IMG3

25

MI0360

R15 0 DGND SGND

10uF C9 DGND 10uF SF_CS

12

DGND DGND

K82*k12*MI1310 PIN1 toward to rightC

Be closed to pin913 14 15 16 17 18 19 20 21 22 23 DGND S_HSYNC SF_SCK S_VSYNC SEN_CLK SF_SO S_PCK VDD18 SCL VDDD SF_SI 24 DGND

Be closed to pin10U7 R10 0 VDDIO_2V8 AAP2968-18VIR1_SOT23 3 C24 10uF C25 0.1uF GND VIN VOUT 2 C31 C32 VDDU

Snap Shot

Normal pull low via 1.5K ohms to DGND Active high.C

VDD_2V8

VDD_1V8 DGND

SDA

4.7uF 0.1UF

VDDD

VDD18

DGND VAA_2V8 R12 0 C27 10uF S_PWR_DN C28 0.1uF

DGND DGND C18 0.1uF C19 0.1uF C20 0.1uF C10 0.1uF C11 0.1uF C12 0.1uF C13 0.1uF C14 0.1uF C15 0.1uF C16 0.1uF C17 0.1uF

GPIO_0△ sensor reset GPIO_1△ key snapshot GPIO_2△ reserved

1

DGND

DGND

DGND

Bypass capacitors of ASICSGND VDD_2V8

Be closed to ASIC

TP2 USB5V USB5V U6 1 1 2 3 C41B

EN1 Vin EN2

Vout1 GND Vout2

6 5 4 C42 10uF C39 0.1uF

USB5V VDD_3V3 U5 VDDD L1 0 C35 C36 0.1uF DGND 10uF DGND VDD_3V3 DGND SF_CS WP HOLD R14 SF_CS SF_SI WP DGND 1 2 3 4 CS# VCC SO HOLD# WP# SCLK GND SI 8 7 6 5 HOLD SF_SCK SF_SO C29 10uF/0805 VDD_3V3

1uF EUP7201-28/33VR1_SOT23-6 DGND TP1 GND

C30 0.1uF DGND

R13 0/0805 JP1+5V DD+ NC GND 1 2 3 4 5 DM DP

B

MX25L512/SOP8 VDD_3V3 100K

DGND

1

VDDU L2 0 C43 10uF C40 0.1uF C37 10uF

CON/mini USB 5pin

Serial FlashC38 0.1uF

DGND

USB connector is better to be closed to SONiX chip. The traces of DM& DP should be straight, short, and parallel.

DGND DGND DGND

A

A

Title

QUADRANT COMPONENTS CO.,LTD.Size C Date: Document Number Rev

SN9C288P+MI1310&1320Friday, January 29, 2010 Sheet 1 of 2

S13

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