AD9516-1BCPZ;AD9516-1BCPZ-REEL7;AD9516-1PCBZ;中文规格书,Data

Data Sheet

FEATURES

Low phase noise, phase-locked loop (PLL)

On-chip VCO tunes from 2.30 GHz to 2.65 GHz External VCO/VCXO to 2.4 GHz optional

1 differential or 2 single-ended reference inputs Reference monitoring capability

Automatic revertive and manual reference switchover/holdover modes

Accepts LVPECL, LVDS, or CMOS references to 250 MHz Programmable delays in path to PFD Digital or analog lock detect, selectable 6 pairs of 1.6 GHz LVPECL outputs

Each output pair shares a 1-to-32 pider with coarse phase delay

Additive output jitter: 225 fs rms

Channel-to-channel skew paired outputs of <10 ps 4 pairs of 800 MHz LVDS clock outputs

Each output pair shares two cascaded 1-to-32 piders with coarse phase delay

Additive output jitter: 275 fs rms

Fine delay adjust (Δt) on each LVDS output

Each LVDS output can be reconfigured as two 250 MHz CMOS outputs

Automatic synchronization of all outputs on power-up Manual output synchronization available 64-lead LFCSP

APPLICATIONS

Low jitter, low phase noise clock distribution

10/40/100 Gb/sec networking line cards, including SONET, Synchronous Ethernet, OTU2/3/4 Forward error correction (G.710)

Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers ATE and high performance instrumentation

GENERAL DESCRIPTION

The AD9516-11 provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 2.30 GHz to 2.65 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz can be used.

The AD9516-1 emphasizes low jitter and phase noise to maximize data converter performance, and it can benefit other applications with demanding phase noise and jitter requirements.

Rev. B

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14-Output Clock Generator with

Integrated 2.5 GHz VCO

AD9516-1

FUNCTIONAL BLOCK DIAGRAM

CP

LF

REFIN

CLK

1

00-02460

Figure 1.

The AD9516-1 features six LVPECL outputs (in three pairs) and four LVDS outputs (in two pairs). Each LVDS output can be reconfigured as two CMOS outputs. The LVPECL outputs

operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and the CMOS outputs operate to 250 MHz.

Each pair of outputs has piders that allow both the pide ratio and coarse delay (or phase) to be set. The range of pision for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs allow a range of pisions up to a maximum of 1024.

The AD9516-1 is available in a 64-lead LFCSP and can be operated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP) to 5 V. A separate LVPECL power supply can be from 2.5 V to 3.3 V (nominal). The AD9516-1 is specified for operation over the industrial range of 40°C to +85°C.

1

AD9516 is used throughout to refer to all the members of the AD9516 family. However, when AD9516-1 is used, it refers to that specific member of the AD9516 family.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781.329.4700 http://www.77cn.com.cn Fax: 781.461.3113 ©2007–2012 Analog Devices, Inc. All rights reserved.

AD9516-1

Data Sheet

Thermal Resistance....................................................................16 ESD Caution................................................................................16 Pin Configuration and Function Descriptions...........................17 Typical Performance Characteristics...........................................19 Terminology....................................................................................25 Detailed Block Diagram................................................................26 Theory of Operation......................................................................27 Operational Configurations......................................................27 Digital Lock Detect (DLD).......................................................36 Clock Distribution.....................................................................40 Reset Modes................................................................................48 Power-Down Modes..................................................................49 Serial Control Port.........................................................................50 Serial Control Port Pin Descriptions.......................................50 General Operation of Serial Control Port...............................50 The Instruction Word (16 Bits)................................................51 MSB/LSB First Transfers...........................................................51 Thermal Performance....................................................................54 Register Map Overview.................................................................55 Register Map Descriptions............................................................59 Applications Information..............................................................77 Frequency Planning Using the AD9516..................................77 Using the AD9516 Outputs for ADC Clock Applications....77 LVPECL …… 此处隐藏：21730字，全部文档内容请下载后查看。喜欢就下载吧 ……