2D-4 Recent Research and Emerging Challenges in Physical Des

As IC process geometries scale down to the nanometer territory, the industry faces severe challenges of manufacturing limitations. To guarantee yield and reliability, physical design for manufacturability and reliability has played a pivotal role in resolu

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RecentResearchandEmergingChallengesinPhysicalDesignfor

Manufacturability/Reliability

Chung-WeiLin1,Ming-ChaoTsai2,Kuang-YaoLee2,Tai-ChenChen1,Ting-ChiWang2,andYao-WenChang1,3

1

GraduateInstituteofElectronicsEngineering,NationalTaiwanUniversity,Taipei106,Taiwan

2

DepartmentofComputerScience,NationalTsingHuaUniversity,Hsinchu300,TaiwanDepartmentofElectricalEngineering,NationalTaiwanUniversity,Taipei106,Taiwan

3

{enorm,tcchen}@eda.ee.ntu.edu.tw,{d938316,d924347}@oz.nthu.edu.tw,tcwang@cs.nthu.edu.tw,andywchang@cc.ee.ntu.edu.tw

ABSTRACT

AsICprocessgeometriesscaledowntothenanometerterritory,theindustryfacesseverechallengesofmanufacturinglimitations.Toguar-anteeyieldandreliability,physicaldesignformanufacturabilityandreli-abilityhasplayedapivotalroleinresolutionandthusyieldenhancementfortheimperfectmanufacturingprocess.Inthispaper,weintroducema-jorchallengesarisingfromnanometerprocesstechnology,surveykeyexistingtechniquesforhandlingthechallenges,andprovidesomefutureresearchdirectionsinphysicaldesignformanufacturabilityandreliabil-ity.

Fig.1(b)

LineI.INTRODUCTION

AsICprocessgeometriesscaledownto90nmandbelow,theindus-tryfacesseverechallengesofmanufacturinglimitations,inducedmainlyfromthelithographiclimitation.Becausetheindustrystilluses193nmlithographytoprintsub-90nmfeaturesize,therearemanyunwantedef-fectsresultinginlargedistortionsfortheshapesonawaferasshowninFigure1(a).Consequently,yieldandreliabilitybecome rst-ordercostmetricsundertheimperfectlithographicprocess.

Toimproveyieldandreliability,resolutionenhancementtechniques(RETs)[39]arenecessary.Thesetechniquesincludeopticalproximitycorrection(OPC),sub-resolutionassistfeature(SRAF,alsocalledscat-teringbar),phase-shiftingmask(PSM),off-axisillumination(OAI),etc.Theycaneffectivelyachievebetterlithographicprintability,buttheircostsareusuallyhigh[30].Forexample,OPCmaygenerateagreatnumberofpolygonsonamask,whilePSMneedtousephaseshiftersatthemasklevel,bothresultinginveryhighmaskcosts.Anotherur-gentissueofRETsisthatitmaybetoolatetoperformRETsafterthephysicaldesignstage.Forexample,ifthereisnoenoughspaceamongwiresafterthephysicaldesignstage,OPCwillprobablyfail.Therefore,physicaldesignformanufacturabilityiscrucialtoensurethesuccessofmanufacturing.

Anotherapproachtoimproveyieldandreliabilityundertheimperfectmanufacturingprocessisphysicaldesignforreliability.Forexample,wirespreadingandwideningcanreducetheprobabilityofshortsandopens,respectively.Besides,inordertoreducetheviafailurecausedbylithographicdistortion,double-viainsertionandline-endextensionarerecommended.Line-endextensionistoextendthelineendsofmetalsforaviaandcanalleviatethevia-cutmisalignmentproblemcausedbyline-endshorting.Ontheotherhand,ifoneviafails,double-viainsertion

workwaspartiallysupportedbyNationalScienceCouncilofTaiwan

underGrantNo’sNSC95-2221-E-002-372,NSC95-2221-E-002-374,NSC95-2752-E-002-008-PAE,NSC95-2220-E-007-037,andMinistryofEconomicAf-fairsofTaiwanunderGrantNo.MOEA95-EC-17-A-01-S1-031.

This

fortheisnotwellofthe(Sec-tionofsomeandII.PHYSICALDESIGNFORMANUFACTURABILITY

Toachievethesuccessofmanufacturing,ithasbeenpointedoutthatlayoutrestrictionsareinevitable[24],andadditionalrestrictedde-signruleshavebeensuggested[12,13,19,22,33],especiallyforarouter[22].Asarelativelynewissue,mostrelatedworksintheliteraturefocusonOPCandPSM,withsomeotherworksconsideringdifferentef-fects.

A.OPC

OPCisprobablythemostpopularRET.Itcandealwithsometypesofimage-shapedistortionssuchaslineshortening,cornerrounding,andline-widthvariationsbyaddingorsubtractingsomefeaturesasserifsorlinesegmentsasshowninFigures1(b)–(d).However,OPCmaygenerateagreatnumberofpolygonswithaveryhighmaskcost,anditmightfailifthereisnoenoughspaceamongwiresafterthephysicaldesignstage.Therefore,afewexistingworkstargetedontheassuranceofOPCsuccessandthereductionofOPCpatternfeatures.

HuangandWong[17]presentedapioneeringworkonOPC-friendlymazeroutingbasedontheLagrangianrelaxationformulation.Therouter

As IC process geometries scale down to the nanometer territory, the industry faces severe challenges of manufacturing limitations. To guarantee yield and reliability, physical design for manufacturability and reliability has played a pivotal role in resolu

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isgrid-basedandconsidersonlytwo-pinconnections.Furthermore,itusesthe atframeworkandthushandlesonlyhundredsofconnections.Wuetal.[41]formulatedtwoOPC-awaremazeroutingproblemsandsolvedthembymodifyingthewell-knownLeealgorithm.Inthiswork,simpleOPCcostsofroutinggridcellsarecalculatedbytheestimatedlightintensitygeneratedbyeachroutednet.

ChenandChang[5]presentedthe rstmultilevel,full-chipgridlessdetailedrouterconsideringtheOPCeffects.Therouterintegratesglobalrouting,detailedrouting,andcongestionestimationtogetherateachlevelofthemultilevelrouting.Itcanhandlenon-uniformwirewidthsandcon-siderroutabilityandOPCsimultaneously.Foreachline,itsOPCcostisde nedasthetotalnumberofpatternfeaturesandappliedamodi edDijkstra’sshortestpathalgorithmtooptimizetheroutingandOPCcostssimultaneously.Experimentalresultsshowthatthisworknotonlyef -cientlyobtainssigni cantlybetterroutingsolutionswith100%routingcompletion,butalsoarchivesaneffectivereductionofOPCpatternfea-tures.

Mitraetal.[28]developedanRET-awaredetailedroutertohandlefull-chipcapacitytoenhancetheoverallprintability.Aftertheinitialroutingresult,afastlithographysimulationisappliedtointroducethelithographyhotspotmap(LHM).AccordingtotheLHM,theroutergen-eratesroutingblockagesforthestageofripupandreroute.Afterwirespreading,ripup,andreroute,thenumberofedgeplacementerror(EPE)hotspotsisreducedby40%.

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